FINITE STATE MACHINE with DATAPATH
SYNTHESIS
Dr. Le Dung
Hanoi University of Science and Technology
FSMD MODEL
Data inputs
Status signals
Controller Controller Control
Datapath
inputs signals
Controller outputs Data outputs
Datapath performs the computations on data
Controller indicates to the datapath which operations have to
be carried out on which data (algorithm)
Dr. Le Dung Hanoi University of Science and Technology
Datapath Design
Temporary storage:
registers, (shift registers), counters, register files, FIFOs, LIFOs
Functional units:
arithmetic units, logical units and (barrel shifter)
Connections:
data busses, multiplexers, tri-state buffers
Shift register (temporary store) Register (temporary store)
Barrel shifter (functional unit)
Dr. Le Dung Hanoi University of Science and Technology
Temporary storage
Inputs Inputs
Reset R Reset R
Register C Clock Up/Down U/D Counter C Clock
Load L Load L
Output Output
Inputs
Read Enable RE
Read Address RA(n) Register
(n bits)
Files C Clock
2n
Write Enable WE
Write Address WA(n)
(n bits)
Output
Dr. Le Dung Hanoi University of Science and Technology
Register Files
Dr. Le Dung Hanoi University of Science and Technology
Functional Units
• Arithmetic units : Adder, Subtractor, Multiplier, Divider
• Logical units : Comparator, AND, OR, XOR …
• Barrel shifter : a digital circuit that can shift a data word
by a specified number of bits in one clock cycle.
Dr. Le Dung Hanoi University of Science and Technology
Eight-bit Barrel Shifter
8 bits input
Shift
Sh
8-bit Barrel shifter
Number (0-7) Nr
8 bits output
Dr. Le Dung Hanoi University of Science and Technology
Generic structure of the Datapath
External inputs
Connections
Temporary storage
Connections Operand switching network
Functional units
Connections Result switching network
External outputs
Dr. Le Dung Hanoi University of Science and Technology
Connections in Datapath
Inputs
k0 k1
S MUX
RE
RA(n) Register R
R
Register C Files C U/D Counter C
L L
2n
WE
WA(n)
ROE COE Data
Tri-buffer
busses
Data
busses
Comparator Sh
F ALU Barrel shifter
< = > Nr Outputs
AOE Tri-buffer BOE
OOE
Dr. Le Dung Hanoi University of Science and Technology
Example 1: Datapath design (1)
• Each variable and constant corresponds to a register or counter
• Each operator corresponds to a functional unit.
Algorithm : Temporary storage:
sum Register
input sum;
i Up counter
FOR i = 1 TO 5
5 Register
input x; x Register
sum = sum + x;
ENDFOR Functional units:
outport sum; + Adder
>5 Comparator
Dr. Le Dung Hanoi University of Science and Technology
Example 1: Datapath design (2)
• Connect outputs of registers and counter to input of functional units
• Connect output of functional units to input of registers and counter
input sum;
FOR i = 1 TO 5
input x; Input
sum = sum + x;
ENDFOR k0 k1
outport sum;
5 1 1 S MUX
Register Up Counter Register Register
5 U
=5 i C x C sum C
1 L 3 L 4 L 2 L
Output
Comparator
Adder
< 6
C
(status)
Dr. Le Dung Hanoi University of Science and Technology
Example 1: Controller design
State A
Input sum; Start=0
FOR i = 1 TO 5 1 = 0 k0
input x; Start=1
sum = sum + x; One-hot FSM
State B
ENDFOR
outport sum; 1 =0 2 3
D-FF design
State C
1 1 =1 4
Start 2
3 0
Controller State D 1 State F
4 1 =1 2 C
C 1 =1 6
5
6
State E
Clk 1 =1 5
Dr. Le Dung Hanoi University of Science and Technology
Example 2: FSMD Design
Dr. Le Dung Hanoi University of Science and Technology
Exercise
Thiết kế Datapath cho FSMD thực hiện thuật toán đếm và tính tổng của
các số lớn hơn 10 trong các số x đựơc đưa vào như sau:
cnt=0; sum=0;
Repeat
input x
if (x> 10) then
cnt=cnt + 1; sum=sum + x;
end if;
until x =0;
output sum; output cnt;
Chú ý: 1. 0 ≤ x ≤255, 0≤ sum ≤255.
Các lệnh viết trên cùng 1 hàng được thực hiện song song.
2. Chỉ rõ các thanh ghi trong datapath là bao nhiêu bit.
Dr. Le Dung Hanoi University of Science and Technology
