© KLMH

VLSI Physical Design: From Graph Partitioning to Timing Closure

Chapter 3 – Chip Planning

Original Authors:
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 1

Lienig
 Chapter 3 – Chip Planning

© KLMH
3.1 Introduction to Floorplanning
3.2 Optimization Goals in Floorplanning
3.3 Terminology
3.4 Floorplan Representations
3.4.1 Floorplan to a Constraint-Graph Pair
3.4.2 Floorplan to a Sequence Pair
3.4.3 Sequence Pair to a Floorplan
3.5 Floorplanning Algorithms
3.5.1 Floorplan Sizing
3.5.2 Cluster Growth
3.5.3 Simulated Annealing
3.5.4 Integrated Floorplanning Algorithms
3.6 Pin Assignment
3.7 Power and Ground Routing
3.7.1 Design of a Power-Ground Distribution Network
3.7.2 Planar Routing
3.7.3 Mesh Routing

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 2

Lienig
 3.1 Introduction

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System Specification

Partitioning
Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design Chip Planning
and Logic Design

Circuit Design Placement

Physical Design
Clock Tree Synthesis

Physical Verification
DRC and Signoff
LVS Signal Routing
ERC
Fabrication

Timing Closure

Packaging and Testing

Chip

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 3

Lienig
 3.1 Introduction

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I/O Pads Floorplan
Module a

Module b
Block a Block c
Module c
GND VDD
Chip Block d
Planning Block Pins
Block
Module d b Block e

Module e

© 2011 Springer Verlag

Supply Network

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 4

Lienig
 3.1 Introduction

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Example
Given: Three blocks with the following potential widths and heights
Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2
Block B: w = 1, h = 2 or w = 2, h = 1
Block C: w = 1, h = 3 or w = 3, h = 1

Task: Floorplan with minimum total area enclosed

C
A B

B
C
A

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 5

Lienig
 3.1 Introduction

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Example
Given: Three blocks with the following potential widths and heights
Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2
Block B: w = 1, h = 2 or w = 2, h = 1
Block C: w = 1, h = 3 or w = 3, h = 1

Task: Floorplan with minimum total area enclosed

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 6

Lienig
 3.1 Introduction

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Example
Given: Three blocks with the following potential widths and heights
Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2
Block B: w = 1, h = 2 or w = 2, h = 1
Block C: w = 1, h = 3 or w = 3, h = 1

Task: Floorplan with minimum total area enclosed

Solution:
Aspect ratios
Block A with w = 2, h = 2; Block B with w = 2, h = 1; Block C with w = 1, h = 3

This floorplan has a global bounding box with minimum possible area (9 square units).

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 7

Lienig
 3.2 Optimization Goals in Floorplanning

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 Area and shape of the global bounding box
 Global bounding box of a floorplan is the minimum axis-aligned rectangle
that contains all floorplan blocks.
 Area of the global bounding box represents the area of the top-level floorplan
 Minimizing the area involves finding (x,y) locations, as well as shapes,
of the individual blocks.
 Total wirelength
 Long connections between blocks may increase signal propagation delays
in the design.
 Combination of area area(F) and total wirelength L(F) of floorplan F
 Minimize  ∙ area(F) + (1 – ) ∙ L(F)
where the parameter 0 ≤  ≤ 1 gives the relative importance between area(F)
and L(F)
 Signal delays
 Static timing analysis is used to identify the interconnects that lie on critical paths.

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 3.3 Terminology

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 A rectangular dissection is a division of the chip area into a set of blocks
or non-overlapping rectangles.

 A slicing floorplan is a rectangular dissection

 Obtained by repeatedly dividing each rectangle, starting with the entire chip area,
into two smaller rectangles
 Horizontal or vertical cut line.

 A slicing tree or slicing floorplan tree is a binary tree with k leaves and k – 1

internal nodes
 Each leaf represents a block
 Each internal node represents a horizontal or vertical cut line.

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 9

Lienig
 3.3 Terminology

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Slicing floorplan and two possible corresponding slicing trees

V V

c H H H H
b

e f a b c a b d

© 2011 Springer Verlag

H H
a
d d V c V

e f e f

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Lienig
 3.3 Terminology

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Polish expression

c H H
b

e f a b c H A B+ C D EF ++ 
a
d d V

e f
 Bottom up: V   and H  +
 Length 2n-1 (n = Number of leaves of the slicing tree)

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Lienig
 3.3 Terminology

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Non-slicing floorplans (wheels)

b b
c a
e e
a c
d d

© 2011 Springer Verlag

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Lienig
 3.3 Terminology

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Floorplan tree: Tree that represents a hierarchical floorplan

d H
b e
g V H
c
a
f H W h i
h
i a b c d e f g

Horizontal division

© 2011 Springer Verlag

H
(objects to the top and bottom)
W
H Wheel (4 objects cycled
V
H Vertical division
(objects to the left and right) around a center object)

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Lienig
 3.3 Terminology

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 In a vertical constraint graph (VCG), node weights represent the heights
of the corresponding blocks.
 Two nodes vi and vj, with corresponding blocks mi and mj, are connected
with a directed edge from vi to vj if mi is below mj.

 In a horizontal constraint graph (HCG), node weights represent the widths

of the corresponding blocks.
 Two nodes vi and vj, with corresponding blocks mi and mj, are connected
with a directed edge from vi to vj if mi is to the left of mj.

 The longest path(s) in the VCG / HCG correspond(s) to the minimum vertical /
horizontal floorplan span required to pack the blocks (floorplan height / width).

 A constraint-graph pair is a floorplan representation that consists of two

directed graphs – vertical constraint graph and horizontal constraint graph –
which capture the relations between block positions.

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Lienig
 3.3 Terminology

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Constraint graphs d t
b
e
g b d e
c
a g
f

h a c f
i
h
b d e Vertical
Constraint
g i Graph
s a c f t
s
h

© 2011 Springer Verlag

i

Horizontal Constraint Graph

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 3.3 Terminology

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Sequence pair

 Two permutations represent geometric relations between every pair of blocks

 Example: (ABDCE, CBAED)

A D
B
E
C

 Horizontal and vertical relations between blocks A and B:

(… A … B … , … A … B …) → A is left of B
(… A … B … , … B … A …) → A is above B
(… B … A … , … A … B …) → A is below B
(… B … A … , … B … A …) → A is right of B

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Lienig
 3.4 Floorplan Representations

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3.1 Introduction to Floorplanning
3.2 Optimization Goals in Floorplanning
3.3 Terminology
3.4 Floorplan Representations
3.4.1 Floorplan to a Constraint-Graph Pair
3.4.2 Floorplan to a Sequence Pair
3.4.3 Sequence Pair to a Floorplan
3.5 Floorplanning Algorithms
3.5.1 Floorplan Sizing
3.5.2 Cluster Growth
3.5.3 Simulated Annealing
3.5.4 Integrated Floorplanning Algorithms
3.6 Pin Assignment
3.7 Power and Ground Routing
3.7.1 Design of a Power-Ground Distribution Network
3.7.2 Planar Routing
3.7.3 Mesh Routing

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Lienig
 3.4.1 Floorplan to a Constraint-Graph Pair

© KLMH
 Create nodes for every block
 In addition, create a source node and a sink one

a b a b
s t
c d e c d e

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Lienig
 3.4.1 Floorplan to a Constraint-Graph Pair

© KLMH
 Create nodes for every block.
 In addition, create a source node and a sink one.
 Add a directed edge (A,B) if Block A is below/left of Block B. (HCG)

a b a b
s t
c d e c d e

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 19

Lienig
 3.4.1 Floorplan to a Constraint-Graph Pair

© KLMH
 Create nodes for every block.
 In addition, create a source node and a sink one.
 Add a directed edge (A,B) if Block A is below/left of Block B. (HCG)
 Remove the redundant edges
that can be derived from other edges by transitivity.

a b a b
s t
c d e c d e

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 20

Lienig
 3.4.2 Floorplan to a Sequence Pair

© KLMH
 Given two blocks A and B with
 Locations: A = (xA,yA) and B = (xB,yB)

 Dimensions: A = (wA,hA) and B = (wB,hB)

 If x A  w A  x B and !( y A  h A  y B or y B  hB  y A ),
then A is left of B
 If y A  h A  y B and !( x A  w A  x B or x B  wB  x A ),
then A is below B

a b
S  : acdbe 
c d e S  : cdaeb 

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Lienig
 3.4.3 Sequence Pair to a Floorplan

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 Start with the bottom left corner
 Define a weighted sequence as a sequence of blocks based on width
 Each block B has its own width w(B)

 Old (traditional) algorithm: find the longest path through edges (O(n2))
 Newer approach: find the longest common subsequence (LCS)
 Given two weighted sequences S1 and S2, the LCS(S1,S2) is the longest
sequence found in both S1 and S2

 The length of LCS(S1,S2) is the sum of weights

 For block placement:

 LCS(S+,S-) returns the x-coordinates of all blocks

 LCS(S+R,S-) returns the y-coordinates of all blocks (S+R is the reverse of S+)

 The
VLSI Physical length
Design: of LCS(S
From Graph +,S
Partitioning -) and
to Timing LCS(S+
Closure
R
,S-) is the widthChapter
and 3:height, respectively
Chip Planning 22

Lienig
 3.4.3 Sequence Pair to a Floorplan

© KLMH
Algorithm: Longest Common Subsequence (LCS)
Input:sequences S1 and S2, weights of n blocks weights
Output: positions of each block positions, total span L

1. for (i = 1 to n) // initialization
2. block_order[S2[i]] = i
3. lengths[i] = 0
4. for (i = 1 to n)
5. block = S1[i] // current block
6. index = block_order[block]
7. positions[block] = lengths[index] // compute block position
8. t_span = positions[block] + weights[block] // finds length of sequence
// from beginning to block
9. for (j = index to n) // update total length
10. if (t_span > lengths[j]) lengths[j] = t_span
11. else break
12. L = lengths[n] // total length is stored here

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Lienig
 3.4.3 Sequence Pair to a Floorplan

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Example: S1 = <acdbe>, S2 = <cdaeb>,
widths[a b c d e] = [8 4 4 4 4], heights[a b c d e] = [4 2 5 5 6]

Find x-coordinates – go by S1’s order:

Initial: block_order[a b c d e] = [3 5 1 2 4], lengths = [0 0 0 0 0]
Iteration 1 – block = a, index = 3:
positions[a] = lengths[3] = 0, t_span = 8, lengths = [0 0 8 8 8]
Iteration 2 – block = c, index = 1:
positions[c] = lengths[1] = 0, t_span = 4, lengths = [4 4 8 8 8]
Iteration 3 – block = d, index = 2:
positions[d] = lengths[2] = 4, t_span = 8, lengths = [4 8 8 8 8]
Iteration 4 – block = b, index = 5:
positions[b] = lengths[5] = 8, t_span = 12, lengths = [4 8 8 8 12]
Iteration 5 – block = e, index = 4:
positions[e] = lengths[4] = 8, t_span = 12, lengths = [4 8 8 12 12]
positions[a b c d e] = [0 8 0 4 8], total_width = lengths[n = 5] = 12
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Lienig
 3.4.3 Sequence Pair to a Floorplan

© KLMH
Example: S1 = <acdbe>, S2 = <cdaeb>,
widths[a b c d e] = [8 4 4 4 4], heights[a b c d e] = [4 2 5 5 6]

Find y-coordinates – go by S1R’s order:

Initial: block_order[a b c d e] = [3 5 1 2 4], lengths = [0 0 0 0 0]
Iteration 1 – block = e, index = 4:
positions[e] = lengths[4] = 0, t_span = 6, lengths = [0 0 0 6 6]
Iteration 2 – block = b, index = 5:
positions[b] = lengths[5] = 6, t_span = 9, lengths = [0 0 0 6 9]
Iteration 3 – block = d, index = 2:
positions[d] = lengths[2] = 0, t_span = 5, lengths = [0 5 5 6 9]
Iteration 4 – block = c, index = 1:
positions[c] = lengths[1] = 0, t_span = 5, lengths = [5 5 5 6 9]
Iteration 5 – block = a, index = 3:
positions[a] = lengths[3] = 5, t_span = 9, lengths = [5 5 9 9 9]
positions[a b c d e] = [5 6 0 0 0], total_height = lengths[n = 5] = 9
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 25

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 3.5 Floorplanning Algorithms

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3.1 Introduction to Floorplanning
3.2 Optimization Goals in Floorplanning
3.3 Terminology
3.4 Floorplan Representations
3.4.1 Floorplan to a Constraint-Graph Pair
3.4.2 Floorplan to a Sequence Pair
3.4.3 Sequence Pair to a Floorplan
3.5 Floorplanning Algorithms
3.5.1 Floorplan Sizing
3.5.2 Cluster Growth
3.5.3 Simulated Annealing
3.5.4 Integrated Floorplanning Algorithms
3.6 Pin Assignment
3.7 Power and Ground Routing
3.7.1 Design of a Power-Ground Distribution Network
3.7.2 Planar Routing
3.7.3 Mesh Routing

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 3.5 Floorplanning Algorithms

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Common Goals

Otten, R.: Efficient Floorplan Optimization. Int. Conf. on Computer Design, 499-502, 1983
 To minimize the total length of interconnect, subject to an upper bound on
the floorplan area

or

 To simultaneously optimize both wire length and area

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 27

Lienig
 3.5.1 Floorplan Sizing

© KLMH
Shape functions

Otten, R.: Efficient Floorplan Optimization. Int. Conf. on Computer Design, 499-502, 1983
h h
Legal shapes Legal shapes

w w

h*w  A
a a Block with minimum width and
height restrictions

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 28

Lienig
 3.5.1 Floorplan Sizing

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Shape functions

Otten, R.: Efficient Floorplan Optimization. Int. Conf. on Computer Design, 499-502, 1983
h h

w w

Discrete (h,w) values Hard library block

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 29

Lienig
 3.5.1 Floorplan Sizing

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Corner points

5 5

2
2
2
w
5 2 5

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 3.5.1 Floorplan Sizing

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Algorithm

This algorithm finds the minimum floorplan area for a given slicing floorplan in
polynomial time. For non-slicing floorplans, the problem is NP-hard.

 Construct the shape functions of all individual blocks

 Bottom up: Determine the shape function of the top-level floorplan

from the shape functions of the individual blocks

 Top down: From the corner point that corresponds to the minimum top-level
floorplan area, trace back to each block’s shape function to find that block’s
dimensions and location.

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Lienig
 3.5.1 Floorplan Sizing – Example

© KLMH
Step 1: Construct the shape functions of the blocks

3
Block A:
5
5
3

Block B:
4
2

2 4

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Lienig
 3.5.1 Floorplan Sizing – Example

© KLMH
Step 1: Construct the shape functions of the blocks

3 h
Block A:
5
5
3
6
5
4
Block B:
4 2
2

2 4 2 3 4 6 w

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 33

Lienig
 3.5.1 Floorplan Sizing – Example

© KLMH
Step 1: Construct the shape functions of the blocks

3 h
Block A:
5
5
3
6

4
Block B:
3
4 2
2

2 4 2 4 5 6 w

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 34

Lienig
 3.5.1 Floorplan Sizing – Example

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Step 1: Construct the shape functions of the blocks

3 h
Block A:
5
5
3
6

4
Block B: hA(w)
4 2
2

2 4 2 6
4 w

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 35

Lienig
 3.5.1 Floorplan Sizing – Example

© KLMH
Step 1: Construct the shape functions of the blocks

3 h
Block A:
5
5
3
6

4
Block B: hA(w)
4 2 hB(w)
2

2 4 2 6
4 w

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 3.5.1 Floorplan Sizing – Example

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Step 2: Determine the shape function of the top-level floorplan (vertical)

6
4
hA(w)
2 hB(w)

2 4 6 w

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 3.5.1 Floorplan Sizing – Example

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Step 2: Determine the shape function of the top-level floorplan (vertical)

6
4
hA(w)
2 hB(w)

2 4 6 w

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 3.5.1 Floorplan Sizing – Example

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Step 2: Determine the shape function of the top-level floorplan (vertical)

h h

8 8

6 6
hC(w)
4 4
hA(w) hA(w)
2 hB(w) 2 hB(w)

2 4 6 w 2 4 6 w

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 39

Lienig
 3.5.1 Floorplan Sizing – Example

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Step 2: Determine the shape function of the top-level floorplan (vertical)

h h

8 8

6 6
hC(w)
4 4
hA(w) hA(w) 5x5
2 hB(w) 2 hB(w)

2 4 6 w 2 4 6 w

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Lienig
 3.5.1 Floorplan Sizing – Example

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Step 2: Determine the shape function of the top-level floorplan (vertical)

3x9
h h

8 8
4x7
6 6
hC(w)
4 4
hA(w) hA(w) 5x5
2 hB(w) 2 hB(w)

2 4 6 w 2 4 6 w

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Lienig
 3.5.1 Floorplan Sizing – Example

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Step 2: Determine the shape function of the top-level floorplan (vertical)

3x9
h h

8 8
4x7
6 6
hC(w)
4 4
hA(w) hA(w) 5x5
2 hB(w) 2 hB(w)

2 4 6 w 2 4 6 w

Minimimum top-level floorplan

with vertical composition
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 42

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 3.5.1 Floorplan Sizing – Example

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Step 2: Determine the shape function of the top-level floorplan (horizontal)

hB(w) hA(w) hB(w) hA(w) hC(w)

h h
5x5

6 6
4 4 7x4

2 2

9x3
2 4 6 8 w 2 4 6 8 w

Minimimum top-level floorplan

with horizontal composition
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 43

Lienig
 3.5.1 Floorplan Sizing – Example

© KLMH
Step 3: Find the individual blocks’ dimensions and locations

(1) Minimum area floorplan: 5 x 5

6

2 4 6 8 w

Horizontal composition

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Lienig
 3.5.1 Floorplan Sizing – Example

© KLMH
Step 3: Find the individual blocks’ dimensions and locations

(1) Minimum area floorplan: 5 x 5

6

2 (2) Derived block dimensions : 2 x 4 and 3 x 5

2 4 6 8 w

Horizontal composition

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 45

Lienig
 3.5.1 Floorplan Sizing – Example

© KLMH
Step 3: Find the individual blocks’ dimensions and locations

(1) Minimum area floorplan: 5 x 5

6 5x5

2 (2) Derived block dimensions : 2 x 4 and 3 x 5

2 4 6 8 w
2x4 3x5
Horizontal composition

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 3.5.1 Floorplan Sizing – Example

© KLMH
5x5

Resulting slicing tree B A

B A

2x4 3x5

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Lienig
 3.5.2 Cluster Growth

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 Iteratively add blocks to the cluster until all blocks are assigned
 Only the different orientations of the blocks instead of the shape / aspect ratio
are taken into account
 Linear ordering to minimize total wirelength of connections between blocks

h h h
Growth
direction
b b
6 6 c

2 a a a
w w w

© 2011 Springer Verlag

4 4 4

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 48

Lienig
 3.5.2 Cluster Growth – Linear Ordering

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 New nets have no pins on any block from the partially-constructed ordering
 Terminating nets have no other incident blocks that are unplaced
 Continuing nets have at least one pin on a block from the partially-constructed
ordering and at least one pin on an unordered block

Terminating nets New nets

Continuing nets

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 49

Lienig
 3.5.2 Cluster Growth – Linear Ordering

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 Gain of each block m is calculated:

Gainm = (Number of terminating nets of m) – (New nets of m)

N1 GainB = 1 – 1 = 0

A B

N4

 The block with the maximum gain is selected to be placed next

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Lienig
 3.5.2 Cluster Growth – Linear Ordering (Example)

© KLMH
N3
N1 N5

A B C D E
N2 N6

N4

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 N3
N1 N5

© KLMH
A B C D E
N2 N6
N4

Iteration Block New Nets Terminating Gain Continuing

# Nets Nets
0 A N1,N2,N3 -- -3 --
1 B N4 N1 0 --
C N5 -- -1 N3
D
Initial block N4Gain of2 terminating-2
,N5,NA6= (Number N nets of A) – (New
-- nets of A)
E -- -2 N3
N5,N6
2 C N5 -- -1 N3
D N5,N6 N2,N4 0 --
E N5,N6 -- -2 N3
3 C -- -- 0 N3,N5
N3 E -- N6 1 N3,N5
4 N1 C N4 -- N5 N3,N5 2 --

A B D E C
N2 N6
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 N3
N1 N5

© KLMH
A B C D E
N2 N6
N4

Iteration Block New Nets Terminating Gain Continuing

# Nets Nets
0 A N1,N2,N3 -- -3 --
1 B N4 N1 0 --
C N5 -- -1 N3
D N4,N5,N6 N2 -2 --
E -- -2 N3
N5,N6
2 C N5 -- -1 N3
D N5,N6 N2,N4 0 --
E N5,N6 -- -2 N3
3 C -- -- 0 N3,N5
N3 E -- N6 1 N3,N5
4 N1 C N4 -- N5 N3,N5 2 --

A B D E C
N2 N6
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 N3
N1 N5

© KLMH
A B C D E
N2 N6
N4

Iteration Block New Nets Terminating Gain Continuing

# Nets Nets
0 A N1,N2,N3 -- -3 --
1 B N4 N1 0 --
C N5 -- -1 N3
D N4,N5,N6 N2 -2 --
E -- -2 N3
N5,N6
2 C N5 -- -1 N3
D N5,N6 N2,N4 0 --
E N5,N6 -- -2 N3
3 C -- -- 0 N3,N5
N3 E -- N6 1 N3,N5
4 N1 C N4 -- N5 N3,N5 2 --

A B D E C
N2 N6
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 N3
N1 N5

© KLMH
A B C D E
N2 N6
N4

Iteration Block New Nets Terminating Gain Continuing

# Nets Nets
0 A N1,N2,N3 -- -3 --
1 B N4 N1 0 --
C N5 -- -1 N3
D N4,N5,N6 N2 -2 --
E -- -2 N3
N5,N6
2 C N5 -- -1 N3
D N5,N6 N2,N4 0 --
E N5,N6 -- -2 N3
3 C -- -- 0 N3,N5
E -- N6 1 N3,N5

© 2011 Springer Verlag

4 C -- N3,N5 2 --

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 3.5.2 Cluster Growth – Linear Ordering (Example)

© KLMH
N3
N1 N5

A B C D E
N2 N6

N4

N3
N1 N4 N5

A B D E C
N2 N6

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 3.5.2 Cluster Growth – Algorithm

© KLMH
Input: set of all blocks M, cost function C
Output: optimized floorplan F based on C

F=Ø
order = LINEAR_ORDERING(M) // generate linear ordering
for (i = 1 to |order|)
curr_block = order[i]
ADD_TO_FLOORPLAN(F,curr_block,C) // find location and orientation
// of curr_block that causes
// smallest increase based on
// C while obeying constraints

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 3.5.2 Cluster Growth

© KLMH
Analysis

 The objective is to minimize the total wirelength of connections blocks

 Though this produces mediocre solutions, the algorithm

is easy to implement and fast.

 Can be used to find the initial floorplan solutions for iterative algorithms
such as simulated annealing.

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 3.5.3 Simulated Annealing

© KLMH
Introduction

 Simulated Annealing (SA) algorithms are iterative in nature.

 Begins with an initial (arbitrary) solution and seeks

to incrementally improve the objective function.

 During each iteration, a local neighborhood of the current solution is

considered. A new candidate solution is formed by a small perturbation
of the current solution.

 Unlike greedy algorithms, SA algorithms can accept candidate solutions

with higher cost.

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 3.5.3 Simulated Annealing

© KLMH
Cost
Initial solution

Local
optimum Global
optimum

Solution states

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 3.5.3 Simulated Annealing

© KLMH
What is annealing?

 Definition (from material science): controlled cooling process

of high-temperature materials to modify their properties.
 Cooling changes material structure from being highly randomized (chaotic)
to being structured (stable).
 The way that atoms settle in low-temperature state is probabilistic in nature.

 Slower cooling has a higher probability of achieving

a perfect lattice with minimum-energy
 Cooling process occurs in steps
 Atoms need enough time to try different structures
 Sometimes, atoms may move across larger distances and
create (intermediate) higher-energy states
 Probability of the accepting higher-energy states decreases with temperature
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 3.5.3 Simulated Annealing

© KLMH
Simulated Annealing

 Generate an initial solution Sinit, and evaluate its cost.

 Generate a new solution Snew by performing a random walk

 Snew is accepted or rejected based on the temperature T

 Higher T means a higher probability to accept Snew if COST(Snew) > COST(Sinit)
 T slowly decreases to form the final solution

 Boltzmann acceptance criterion, where r is a random number [0,1)

COST ( S init ) COST ( S new )
e T r

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 3.5.3 Simulated Annealing

© KLMH
Simulated Annealing

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 63

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 3.5.3 Simulated Annealing – Algorithm

© KLMH
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 64

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 3.5.3 Simulated Annealing – Algorithm

Input: initial solution init_sol

© KLMH
Output: optimized new solution curr_sol

T = T0 // initialization
i=0
curr_sol = init_sol
curr_cost = COST(curr_sol)
while (T > Tmin)
while (stopping criterion is not met)
i=i+1
(ai,bi) = SELECT_PAIR(curr_sol) // select two objects to perturb
trial_sol = TRY_MOVE(ai,bi) // try small local change
trial_cost = COST(trial_sol)
cost = trial_cost – curr_cost
if (cost < 0) // if there is improvement,
curr_cost = trial_cost // update the cost and
curr_sol = MOVE(ai,bi) // execute the move
else

© 2011 Springer Verlag

r = RANDOM(0,1) // random number [0,1]
if (r < e –Δcost/T) // if it meets threshold,
curr_cost = trial_cost // update the cost and
curr_sol = MOVE(ai,bi) // execute the move
T=α∙T // 0 < α < 1, T reduction
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 3.6 Pin Assignment

© KLMH
3.1 Introduction to Floorplanning
3.2 Optimization Goals in Floorplanning
3.3 Terminology
3.4 Floorplan Representations
3.4.1 Floorplan to a Constraint-Graph Pair
3.4.2 Floorplan to a Sequence Pair
3.4.3 Sequence Pair to a Floorplan
3.5 Floorplanning Algorithms
3.5.1 Floorplan Sizing
3.5.2 Cluster Growth
3.5.3 Simulated Annealing
3.5.4 Integrated Floorplanning Algorithms
3.6 Pin Assignment
3.7 Power and Ground Routing
3.7.1 Design of a Power-Ground Distribution Network
3.7.2 Planar Routing
3.7.3 Mesh Routing

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 3.6 Pin Assignment

© KLMH
During pin assignment, all nets (signals) are assigned to unique pin locations
such that the overall design performance is optimized.

Pin
Assignment
90 Pins 90 Pins

90 Connections

90 Pins 90 Pins

© 2011 Springer Verlag

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 3.6 Pin Assignment – Example

© KLMH
Given: Two sets of pins (1) Determine the circles

Koren, N. L.: Pin Assignment in Automated Printed Circuit Boards

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 3.6 Pin Assignment – Example

© KLMH
(2) Determine the points

Koren, N. L.: Pin Assignment in Automated Printed Circuit Boards

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 3.6 Pin Assignment – Example

© KLMH
(2) Determine the points

Koren, N. L.: Pin Assignment in Automated Printed Circuit Boards

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 3.6 Pin Assignment – Example

© KLMH
(3) Determine initial mapping

Koren, N. L.: Pin Assignment in Automated Printed Circuit Boards

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 3.6 Pin Assignment – Example

© KLMH
(3) Determine initial mapping and (4) optimize the mapping (complete rotation)

Koren, N. L.: Pin Assignment in Automated Printed Circuit Boards

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 3.6 Pin Assignment – Example

© KLMH
(3) Determine initial mapping and (4) optimize the mapping (complete rotation)

Koren, N. L.: Pin Assignment in Automated Printed Circuit Boards

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 3.6 Pin Assignment – Example

© KLMH
(4) Best mapping (shortest Euclidean distance)

Koren, N. L.: Pin Assignment in Automated Printed Circuit Boards

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 3.6 Pin Assignment – Example

© KLMH
(4) Best mapping Final pin assignment

Koren, N. L.: Pin Assignment in Automated Printed Circuit Boards

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 3.6 Pin Assignment

© KLMH
Pin assignment to an external block B

H. N. Brady, “An Approach to Topological Pin Assignment”, IEEE Trans. on CAD 3(3) (1984), pp. 250-255
B B B

m m m

l’

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 3.6 Pin Assignment

© KLMH
Pin assignment to two external blocks A and B

H. N. Brady, “An Approach to Topological Pin Assignment”, IEEE Trans. on CAD 3(3) (1984), pp. 250-255
a7 a6
a5 a8
a8
a7
a a4 b7 b6

1
~d
a1 a6

2
d
b b5 a5
a2 a3 8 b
b1 b4 a4
b8
b2 b3
b7
b6

3
~d
lm~a b5

3
d
b4
b3
d1 a b2
b1
lm~b m
d2 d3 a3
2
~d

b
a2
1
d

m a1
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 3.7 Power and Ground Routing

© KLMH
3.1 Introduction to Floorplanning
3.2 Optimization Goals in Floorplanning
3.3 Terminology
3.4 Floorplan Representations
3.4.1 Floorplan to a Constraint-Graph Pair
3.4.2 Floorplan to a Sequence Pair
3.4.3 Sequence Pair to a Floorplan
3.5 Floorplanning Algorithms
3.5.1 Floorplan Sizing
3.5.2 Cluster Growth
3.5.3 Simulated Annealing
3.5.4 Integrated Floorplanning Algorithms
3.6 Pin Assignment
3.7 Power and Ground Routing
3.7.1 Design of a Power-Ground Distribution Network
3.7.2 Planar Routing
3.7.3 Mesh Routing

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 3.7 Power and Ground Routing

© KLMH
Power-ground distribution for a chip floorplan

G V G V

Power and ground rings

V
V G
per block or abutted blocks

G
V G

V
V

G
G V G V G V

© 2011 Springer Verlag

Trunks connect rings to each
other or to top-level power ring

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 3.7 Power and Ground Routing

© KLMH
Planar routing

GND VDD

© 2011 Springer Verlag

Hamiltonian path

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 3.7 Power and Ground Routing

© KLMH
Planar routing

Step 1: Planarize the topology of the nets

 As both power and ground nets must be routed on one layer,
the design should be split using the Hamiltonian path

Step 2: Layer assignment

 Net segments are assigned to appropriate routing layers

Step 3: Determining the widths of the net segments

 A segment’s width is determined from the sum of the currents
from all the cells to which it connects

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 3.7 Power and Ground Routing

© KLMH
Planar routing

GND VDD

© 2011 Springer Verlag

Generating topology Adjusting widths of the segments
of the two supply nets with regard to their current loads

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 3.7 Power and Ground Routing

© KLMH
Mesh routing

Step 1: Creating a ring

 A ring is constructed to surround the entire core area of the chip,
and possibly individual blocks.

Step 2: Connecting I/O pads to the ring

Step 3: Creating a mesh

 A power mesh consists of a set of stripes at defined pitches on two or more layers

Step 4: Creating Metal1 rails

 Power mesh consists of a set of stripes at defined pitches on two or more layers

Step 5: Connecting the Metal1 rails to the mesh

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 3.7 Power and Ground Routing

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Mesh routing

Connector
Power rail

© 2011 Springer Verlag

Ring Pad Mesh

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 3.7 Power and Ground Routing

© KLMH
Mesh routing

1 Metal4 mesh 2 Metal6 mesh 4 Metal8 mesh

1 Metal5 4 Metal7
16
mesh mesh 16
16

Metal1
rail
VDD GND
Metal4 mesh Metal4 mesh
Metal4

© 2011 Springer Verlag

Via3 Metal6
Metal3 Metal8
Via2 Via5 Via7
Metal2 GND rail Metal5 Metal7
Via1 Via4 Via6
Metal1 VDD rail Metal4 Metal6

M1-to-M4 connection M4-to-M6 connection M6-to-M8 connection

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 Summary of Chapter 3 – Objectives and Terminology

© KLMH
 Traditional floorplanning
 Assumes area estimates for top-level circuit modules
 Determines shapes and locations of circuit modules
 Minimizes chip area and length of global interconnect
 Additional aspects
 Assigning/placing I/O pads
 Defining channels between blocks for routing and buffering
 Design of power and ground networks
 Estimation and optimization of chip timing and routing congestion
 Fixed-outline floorplanning
 Chip size is fixed, focus on interconnect optimization
 Can be applied to individual chip partitions (hierarchically)
 Structure and types of floorplans
 Slicing versus non-slicing, the wheels
 Hierarchical
 Packed
 Zero-deadspace
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 Summary of Chapter 3 – Data Structures for Floorplanning

© KLMH
 Slicing trees and Polish expressions
 Evaluating a floorplan represented by a Polish expression
 Horizontal and vertical constraint graphs
 A data structure to capture (non-slicing) floorplans
 Longest paths determine floorplan dimensions
 Sequence pair
 An array-based data structure that captures the information
 contained in H+V constraint graphs
 Makes constraint graphs unnecessary in practice
 Floorplan sizing
 Shape-function arithmetic
 An algorithm for slicing floorplans

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 Summary of Chapter 3 – Algorithms for Floorplanning

© KLMH
 Cluster growth
 Simple, fast and intuitive
 Not competitive in practice
 Simulated annealing
 Stochastic optimization with hill-climbing
 Many details required for high-quality implementation (e.g., temperature schedule)
 Difficult to debug, fairly slow
 Competitive in practice
 Pin assignment
 Peripheral I/Os versus area-array I/Os
 Given "ideal locations", project them onto perimeter and shift around,
while preserving initial ordering
 Power and ground routing
 Planar routing in channels between blocks
 Can form rings around blocks to increase current supplied and to improve reliability
 Mesh routing

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