Lecture 7

INTERRUPT
&
PIC 8259
Interrupt :
INTERRUPTS
An interrupt is an event which informs the CPU that its service
(action) is needed.
The process starts from the I/O device
The process is asynchronous.
Classification of Interrupts
Interrupts can be classified into two types:
Maskable Interrupts (Can be delayed or Rejected)
Non-Maskable Interrupts (Can not be delayed or
Rejected)
Interrupts can also be classified into:
Vectored (the address of the service routine is hard-wired)
Non-vectored (the address of the service routine needs to
be supplied externally by the device)
Basic Procedure for Processing
Interrupts
When an interrupt is executed, the p:
 finishes executing its current instruction (if any).
 Saves (PUSH) the flag register, IP and CS register
in the stack.
 Goes to a fixed memory location.
 Reads the address of the associated ISR.
 Jumps to that address and executes the ISR.
 Gets (PULL) the flag register, CS:IP register from
the stack.
 Continues executing the previous job (if any).
8086 INTERRUPT CATAGORIES
Interrupt can divide to five groups:
i. Hardware interrupt
ii. Non-maskable interrupt
iii. Software interrupt
iv. Internal interrupt
v. Reset
In the 8086 there are a total of 256 interrupts (or interrupt types):
-INT 00H
-INT 01H
-……….
-INT FFH
For every interrupt there must be a program associated with it .
This program is called Interrupt Service Routine (ISR) .
 It is also called an interrupt handler.
 But where the interrupt handler.
-- In the Interrupt Vector Table (IVT).
The Operation of Real Mode Interrupt:
1. The contents of the flag register are pushed onto the stack.
2. Both the interrupt (IF) and trap (TF) flags are cleared.This
disables the INTR pin and the trap or single step feature.
3. The contents of the code segment register (CS) are pushed onto
the stack.
4. The contents of the instruction pointer (IP) are pushed onto the
stack.
5. The interrupt vector contents are fetched, and then placed into
both IP and CS so that the next instruction executes at the
interrupt service procedure addressed by the vector.
Type 0 interrupts: This interrupt is also known as the divide
by zero interrupt. For cases where the quotient becomes
particularly large to be placed / adjusted an error might occur.
Type 1 interrupts: This is also known as the single step

interrupt. This type of interrupt is primarily used for debugging
purposes in assembly language.
Type 2 interrupts: also known as the non-maskable NMI
interrupts. These type of interrupts are used for emergency
scenarios such as power failure.
Type 3 interrupts: These type of interrupts are also known as
breakpoint interrupts. When this interrupt occurs a program
would execute up to its break point.
Type 4 interrupts: Also known as overflow interrupts is
generally existent after an arithmetic operation was performed.
Programmable Interrupt Controller
8259
PIC 8259
The Programmable Interrupt Controller (PlC) functions

as an overall manager in an Interrupt-Driven system.
It accepts requests from the peripheral equipment,

determines which of the incoming requests is of the
highest importance (priority), ascertains whether the
incoming request has a higher priority value than the
level currently being serviced, and issues an interrupt to
the CPU based on this determination.
CONT’D…
Each peripheral device or structure usually has a special

program or “routine” that is associated with its specific
functional or operational requirements this is referred to
as a “service routine”.
The PlC, after issuing an interrupt to the CPU, must

somehow input information into the CPU that can point
(vector) the Program Counter to the service routine
associated with the requesting device
CONT’D…
The PIC manages eight levels of requests and has built-

in features for expandability to other PIC (up to 64
levels). It is programmed by system software as an I/O
peripheral.
The priority modes can be changed or reconfigured

dynamically at any time during main program operation
.
ARCHITECURE
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
Interrupt Request Register (IRR) and In-Service

Register (ISR)
The interrupts at the IR input lines are

handled by two registers in cascade, the Interrupt
Request Register (lRR) and the In- Service Register
(lSR). The IRR is used to indicate all the interrupt
levels which are requesting service, and the ISR is
used to store all the interrupt levels which are
currently being serviced.
CONT’D…
Priority Resolver
This logic block determines the

priorities of the bits set in the lRR. The highest
priority is selected and strobed into the
corresponding bit of the lSR during the INTA
sequence.
CONT’D…
Interrupt Mask Register (IMR)
The lMR stores the bits which disable

the interrupt lines to be masked. The IMR
operates on the output of the IRR. Masking of a
higher priority input will not affect the interrupt
request lines of lower priority.
CONT’D
Data Bus Buffer
This 3-state, bidirectional 8-bit buffer is

used to interface the PIC to the System Data Bus.
Control words and status information are transferred
through the Data Bus Buffer.
CONT’D…
 Read/Write Control Logic
The function of this block is to accept output commands from

the CPU. It contains the Initialization Command Word (lCW)
registers and Operation Command Word (OCW) registers which
store the various control formats for device operation.
This function block also allows the status of the PIC to be

transferred onto the Data Bus. This function block stores and
compares the IDs of all PICs used in the system.
The associated three I/O pins (CAS0- 2) are outputs when the
8259 is used as a master and are inputs when the 8259 is used as a
slave. As a master, the 8259 sends the ID of the interrupting slave
device onto the CAS0 - 2 lines. The slave, thus selected will send its
preprogrammed subroutine address onto the Data Bus during the
next one or two consecutive INTA pulses.
PIN DIAGRAM
8259 PINS
D[7..0] These wires are connected to the system

bus and are used by the microprocessor to write or
read the internal registers of the 8259.
A[0..0] This pin acts in conjunction with

WR/RD signals. It is used by the 8259 to decipher
various command words the microprocessor writes
and status the microprocessor wishes to read.
CONT’D…
 WR When this write signal is asserted, the 8259
accepts the command on the data line, i.e., the microprocessor
writes to the 8259 by placing a command on the data lines and
asserting this signal.
 RD When this read signal is asserted, the 8259

provides on the data lines its status, i.e., the microprocessor
reads the status of the 8259 by asserting this signal and
reading the data lines.
 INT This signal is asserted whenever a valid interrupt

request is received by the 8259, i.e., it is used to interrupt the
microprocessor.
CONT’D…
 INTA This signal, is used to enable 8259 interrupt-
vector data onto the data bus by a sequence of interrupt
acknowledge pulses issued by the microprocessor.
 IR 0,1,2,3,4,5,6,7 An interrupt request is executed

by a peripheral device when one of these signals is
asserted.
 CAS[2..0] These are cascade signals to enable

multiple 8259 chips to be chained together.
 SP/EN This function is used in conjunction with the

CAS signals for cascading purposes

Lecture 7

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Lecture 7

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INTERRUPT

Interrupt can divide to five groups:

ii. Non-maskable interrupt

iii. Software interrupt

iv. Internal interrupt

Type 1 interrupts: This is also known as the single step

The Programmable Interrupt Controller (PlC) functions

It accepts requests from the peripheral equipment,

Each peripheral device or structure usually has a special

The PlC, after issuing an interrupt to the CPU, must

The PIC manages eight levels of requests and has built-

The priority modes can be changed or reconfigured

Interrupt Request Register (IRR) and In-Service

The interrupts at the IR input lines are

This logic block determines the

Interrupt Mask Register (IMR)

The lMR stores the bits which disable

Data Bus Buffer

This 3-state, bidirectional 8-bit buffer is

The function of this block is to accept output commands from

This function block also allows the status of the PIC to be

D[7..0] These wires are connected to the system

A[0..0] This pin acts in conjunction with

 RD When this read signal is asserted, the 8259

 INT This signal is asserted whenever a valid interrupt

 IR 0,1,2,3,4,5,6,7 An interrupt request is executed

 CAS[2..0] These are cascade signals to enable

 SP/EN This function is used in conjunction with the

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