A SIMPLE PRESENTATION ON

CENTRAL PROCESSING UNIT

Submitted by MESKATUL ISLAM Submitted to MR. MD. NEAMUL HOQUE

ID: 1703210201349 Lecturer, Dept of CSE
8.1: CPU
The central processing unit (CPU) is the portion of a computer system
that carries out the instructions of a computer program, to perform the
basic arithmetical, logical and input-output operations of the system. it
acts as the brain of computer

The CPU is made up of three major parts:

• The registers set stores intermediate data used during the execution
of the instructions.
• The arithmetic logic unit (ALU) performs the required microoperations
for executing the instructions.
• The control unit supervises the transfer of information among the
registers and instructs the ALU as to which operation perform
8.1: CPU (Cont.)

Fig: Major components of CPU

8.2: General Register Organization

 Register:
• Memory locations are needed for storing pointers, counters, return
address, temporary results, and partial products during
multiplication.
• Memory access is the most time-consuming operation in a
computer.
• More convenient and efficient way is to store intermediate values
in processor registers.
8.2: General Register Organization

 Bus System:
• 2 MUX: The output of each register is connected to two
multiplexers (MUX) to from the two buses A and B.
• BUS (A&B): The A and B buses form the inputs to a common ALU.
• ALU: Determines the arithmetic or logic micro-operation.
• Decoder (3X8): The decoder activates one of the register load
inputs, thus providing a transfer path between the data in the
output bus and the inputs of the selected destination register.
• The register that receives the information from the output bus is
selected by a decoder.
8.2: General Register Organization

 Binary selection variables:

• MUX A selector (SELA): to place the content
of R2 into bus A.
• MUX B selector (SELB): to place the content
o f R 3 into bus B.
• ALU operation selector (OPR): to provide the
arithmetic addition A + B.
• Decoder destination selector (SELD): to
transfer the content of the output bus into
R1.
8.2: General Register Organization

 Control Word
• 14 bit control word:
- SELA (3 bits): select a source register for the A input of the ALU
- SELB (3bits): select a source register for the B input of the ALU
- SELD (3 bits): select a destination register using the 3x8 decoder
- OPR (5 bits): select one of the operation in the ALU
• Encoding of ALU Operation (OPR):
- SELA or SELB = 00 (input): MUX selects the external input data
- SELD = 000 (none): no destination register is selected but the
contents of the output bus are available in the external output.
8.2: General Register Organization
8.3: Stack Organization

 Stack: A stack is a storage device that stores information in

such a manner that the item stored last is the first item
retrieved.
• Stack Pointer (SP): The register that holds the address for
the stack. SP always points at the top item in the stack.
• Two operations of a stack: PUSH (insertion) & POP
(deletion)
• Two types of a stack: Register Stack & Memory Stack
8.3: Stack Organization
 Register Stack: A stack can be placed in a portion of a
large memory or it can be organized as a collection of
a finite number of a memory words or registers. This
figure shows the organization of a 64-word register
stack.
PUSH: SP ← SP + 1 :Increment SP
M[SP] ← DR :Write to the stack
If (SP = 0) then (FULL ← 1) :Check if stack is full
EMTY ← 0 :Mark not empty
POP: DR ← M[SP] :Read item from the top of stack
SP ← SP-1 :Decrement stack pointer
If(SP = 0) then (EMTY ←1) :Check if stack is empty
FULL ← 0 :Mark not full
8.3: Stack Organization
 Memory Stack: A stack can exist as a stand alone. The implementation of
a stack in the CPU is done by assigning a portion of memory to a stack
operation & using a processor register as a stack pointer.
PUSH:
SP ← SP - 1
M[SP] ← DR
POP:
DR ← M[SP]
SP ← SP+1
8.3: Stack Organization

 Stack Limits: The stack limit can be checked by using two processor
registers:
- One to hold the upper limit
- And other to hold her lower limit

PUSH: After PUSH operation SP compared with the upper limit register
POP: After a POP operation SP is compared with the lower limit register
8.3: Stack Organization

 Reverse Polish Notation: The common mathematical method of writing

arithmetic expressions imposes difficulties when evaluated by a
computer. A stack organization is very effective for evaluating
arithmetic expressions

A+B Infix Notation

+AB Prefix or Polish Notation
AB+ Postfix reverse Polish Notation
8.4: Instruction Format
 Common fields in instruction formats:
- Operation code field: specify the operation to be performed
- Address field: designate a memory address or a processor register
- Mode field: specify the operand or the effective address
 Three types of CPU organizations:
- Single accumulator organization: ADD X //AC ←AC+M[X]
- General register organization: ADD R1, R2, R3 //R1 ←R2+R3
- Stack organization: PUSH X //TOS ←M[X]

 Three address instruction of X = (A+B)*(C+D)

ADD R1, A, B //R1 → M[A]+M[B]
ADD R2, C, D //R2 → M[C]+M[D]
MUL X, R1, R2 //R1*R2 → M[X]
8.4: Instruction Format
 Two address instruction
MOV R1, A //R1 → M[A]
ADD R1, B //R1 → R1+M[B]
MOV R2, C //R2 → M[C]
ADD R2, D //R2 →R2+M[D]
MUL R1, R2 //R1 →R1*R2
MOV X, R1 //R1 → M[X]
 One address instruction
LOAD A //M[A] →AC
ADD B //AC-M[B] →AC
STORE T //AC →M[T]
LOAD C //M[C] →AC
ADD D //AC+M[D] →AC
MUL T //AC*M[T] →AC
STORE X //AC →M[X]
8.4: Instruction Format
 Zero address instruction
PUSH A //A →TOS
PUSH B //B→TOS
ADD //(A+B) →TOS
PUSH C //C →TOS
PUSH D //D →TOS
ADD //(C+D) →TOS
MUL //(A+B)*(C+D) →TOS
POP X //TOS →M[X]
 RISC instruction: only use LOAD and STORE instruction when
communicating between memory and CPU. All other instructions are
executed within the registers of the CPU without referring to memory
8.4: Instruction Format
RISC Instruction Example:
8.5: Addressing Modes

 Purpose of addressing modes:

1. To give programming versatility to the user by providing such facilities as
pointers to memory, counters for loop control, indexing of data, and
program relocation.
2. To reduce the number of bits in the addressing field of the instruction.
 Instruction Cycle:
1. Fetch the instruction from memory
2. Decode the instruction
3. Execute the instruction
 Addressing mode of the instruction:
1. Distinct Binary Code
2. Single Binary Code
8.5: Addressing Modes
 Instruction Format:

 Implied mode: Operands are specified implicitly in the instruction.

- Complement Accumulator (COM): Operand in AC is implied in the definition of
the instruction.
- Stack Push (PUSH): Operand is implied to be on top of the stack.
 Immediate mode: Operand is specified in the instruction itself.
MOV R1, #100
 Register mode: Operands are in the registers within the CPU.
MOV R1, R2
8.5: Addressing Modes
 Register Indirect Mode: Instruction specifies a register whose contents give
the address of the operand in memory.
- The address field of the instruction uses fewer bits to select a register than
would have been required to specify a memory address
 Auto increment or decrement mode: Similar to register indirect mode
except that the register is incremented or decremented after or before its
value is used to access memory.
MOV (R1 ++), (R2 ++)
 Direct mode: Effective address is equal to the address field of the instruction
(Operand). Address field specifies the actual branch address in a branch-type
instruction.
 Indirect mode: Address field of instruction gives the address where the
effective address is stored in memory.
8.5: Addressing Modes

 Relative Mode: Program counter is added to the address part of the

instruction to obtain the effective address.
 Indexed Mode: Index register is added to the address part of the
instruction to obtain the effective address.
 Base Register mode: The content of a base register is added to the
address part of the instruction to obtain the effective address. Similar
to the indexed addressing mode except that the register is now called a
base register instead of an index register
8.6: Data transfer and manipulation

 Most computer instruction can be classified into three categories:

1. Data transfer instructions
2. Data manipulation instructions
3. Program control instructions
 Data transfer Instruction:
Typical data transfer instruction 8 Addressing mode for the LOAD instruction
8.6: Data transfer and manipulation

 Data manipulation instruction: Three basic type

1. Arithmetic instructions
INC, DEC, ADD, MUL, NEG, etc.
2. Logical and bit manipulation instructions
CLR, COM, AND, OR, XOR, etc.
3. Shift instructions
SHR, SHL, ROR, ROL, etc.
8.7: Program Control
 Program Control Instruction: Branch and jump
instructions are interchangeably to mean the
same thing.
 Status Bit Conditions: condition code or flag
bits
- C (carry): 1 if the end carry C8 is 1
- S (sign): 1 if the MSB F7 is 1
- Z (zero): 1 if the output of ALU contains all
0’s
- V (overflow): 1 if the Exclusive-OR of last
two carry is 1
8.7: Program Control
 Conditional Branch Instructions:
BZ Branch in zero // Z=1
BNZ Branch in not zero // Z=0
BC Branch if carry //C=1
BNV Branch if not overflow//V=0
-Example (A(11110000) – B(00010100))
8.7: Program Control
 Subroutine Call and Return:
- Call: A subroutine call is implemented with the following microoperations:

- Return:
8.7: Program Control
 Program Interrupt:
- Types of interrupts
- External interrupts: I/O device, timer etc.
- Internal interrupts: illegal instruction or data
- Software interrupts: special call instruction that behaviors like an interrupt
rather than a subroutine call
- The state of the CPU which must be saved
- The content of the program counter
- The content of all processor registers
- The content of certain status conditions
- The CPU does not respond to an interrupt until end of an instruction execution
8.8: Reduced Instruction Set Computer (RISC)
 CISC characteristics:
- A large number of instruction (100 to 250)
- Some instructions that perform specialized tasks and are used infrequently
- A large variety of addressing modes (5 to 20)
- Variable-length instruction formats
- Instructions that manipulate operands in memory
 CRSC characteristics:
- Reality few instructions
- Reality few addressing modes
- Memory access limited to load and store instructions
- All operations done within the registers of the CPU
- Fixed-length, easily decoded instruction formats
- Single-cycle instruction execution
- Hardwired rather than microprogrammed control
8.8: Reduced Instruction Set Computer (RISC)
 Overlapped register windows:
- To avoid the need for saving and restoring register values and to provides the
passing of parameters when procedure call and return.
- Local registers are used for local variables. Common registers are used for
exchange of parameters and results between adjacent procedures.
- Only one register window is activated at any given time with a pointer
indicating the active window
- G = the number of global registers
- L = the number of local registers in each window
- C = the number of registers common to two windows
- W = the number of windows
- Windows size = L+2C+G
- Register file = (L+C)W+G
8.8: Reduced Instruction Set Computer (RISC)
 THANK YOU!
Reference:
Online Class Lectures Video,
Computer System Architecture(M.M. Mano),
tutorialspoint.com, Google, Wikipedia etc.