DEPARTMENT OF COMPUTING AND INFORMATION

TECHNOLOGY

Lesson 1: Logic Gates

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 Definition:
• The logic gate is the basic building block in digital
systems used to implement Boolean function.
• Logic gates operate with binary numbers (1/0).
They are are therefore referred to as binary logic
gates
• Basic logic circuits with one or more inputs and one
output are known as gates
• Gates are used as the building blocks in the design
of more complex digital logic circuits
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 Representing Logic Functions
• There are several ways of representing logic
functions:
– Symbols to represent the gates/ Logic
symbol
– Truth tables
– Boolean algebra
We will now describe commonly used gates

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 Logic 0 vs Logic 1
• Logic 0 is the same as • Logic 1 is the same as
– FALSE – TRUE
– OFF – ON
– LOW – HIGH
– NO – YES
– OPEN SWITCH – CLOSED SWITCH

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 NOT Gate (INVERTER)
Symbol
Truth-table Boolean
y=a
a y Input Output
a y
0 1
1 0

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 AND Gate
Symbol Truth-table Boolean
a y a b y
0 0 0 y = a.b
b
0 1 0
1 0 0
1 1 1

• y is only TRUE only if a is TRUE and b is TRUE.

• AND gate is a circuit that operates such that its output is
logic 1 (HIGH) only when ALL its inputs are HIGH
• Has a minimum of two inputs and maximum of 8 inputs
• For all other cases the AND gate’s output is LOW
• Note that in Boolean algebra AND is represented by a dot .
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 OR Gate
Symbol Truth-table Boolean

a
y=a+b
a b not read as a plus b
b
0 0 0
0 1 1
1 0 1
1 1 1

• y is TRUE if a is TRUE or b is TRUE (or both) but FALSE

when both inputs are FALSE
• It has two or more inputs and one output
• In Boolean algebra OR is represented by a plus sign +

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 UNIVERSAL GATES
• A universal gate is a gate which can implement any Boolean
function without need to use any other gate type.
• The NAND and NOR gates are universal gates.
• Y=A+B
• In practice, this is advantageous since NAND and NOR gates
are economical and easier to fabricate and are the basic gates
used in all IC digital logic families. In fact, an AND gate is
typically implemented as a NAND gate followed by an inverter
not the other way around!!
• Likewise, an OR gate is typically implemented as a NOR gate
followed by an inverter not the other way around!!
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9
 NOT AND (NAND) Gate

y = a.b

0 0 1
0 1 1
1 0 1
1 1 0

• y is TRUE if a is FALSE or b is FALSE (or both)

• y is FALSE only if a is TRUE and b is TRUE
• It is the same as the AND gate symbol except for the small
circle on its output. Once again the small circle denotes
the inversion operation
• Thus the NAND gate operates like an AND gate followed
by INVERTER 10
 NOT OR (NOR) Gate
a b y y=a+b
0 0 1
0 1 0
1 0 0
1 1 0

• y is TRUE only if a is FALSE and b is FALSE

• y is FALSE if a is TRUE or b is TRUE (or both)
• It is a combination of an OR function and a NOT function.
• It is realized by connecting a NOT gate to the output of an
OR gate.

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 EXCLUSIVE OR (XOR) Gate

a a b y y=a b
y 0 0 0
b 0 1 1
1 0 1
1 1 0

• y is TRUE if a is TRUE or b is TRUE (but not both)

• In Boolean algebra XOR is represented by an sign
• Note that its truth table is almost the same as that of OR
except for the last entry in the truth table where both inputs
are HIGH
• When the inputs are equal the output goes LOW and when
the input differ the output is HIGH. This characteristic gives
the gate the name of an inequality comparator
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 EXCLUSIVE NOR (XNOR) Gate

a a b y y=a b
y 0 0 1
b 0 1 0
1 0 0
1 1 1

• y is TRUE if both a and b are TRUE or when both are FALSE

• From the truth table when the inputs are not the same the output is
LOW/FALSE otherwise the output will be HIGH/TRUE. This gives
the gate the characteristic equality comparator

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Lesson 2

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 LAWS AND RULES OF BOOLEAN
ALGEBRA
• Boolean algebra is used to express logic
circuits mathematically.
• It is used to simplify logic circuits thus
minimizes amount of logic gates used to
perform a specific function

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 Rules of Boolean Algebra
• There are 14 basic rules that are useful in
manipulating and simplifying Boolean
expressions. Rules 1 through 9 will be viewed
in terms of their application to logic gates.
Rules 10 through 14 can be derived in terms
of the simpler rules and the laws previously
discussed

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 Basic rules of Boolean algebra
1. A+0=A
2. A+1=1
3. A.0 = 0
4. A.1 = A
5. A+A=A
6. A+A=1
7. A.A = A
8. A. A = 0
9.
A =A
10. A + AB = A
11. A+AB=A+B
12 (A + B) (A+C) = A + BC

13 AB + A’C + BC = AB + A’C
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14 (A+B)(A’+C)(B+C)=(A+B)(A’+C)
 Proof of rules 10,11 & 12
Rule 10
A + AB = A
We use rule 2, 4 and distributive law to prove
the left side
A + AB
=A.1 + A.B
=A(1+B), Distributive law, rule 2
=A.1, rule 2
=A , rule 4
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Rule 11
A + A’B = A + B
Left side A + A’B
= A.1 + A’B, rule 4
= A(1+B) + A’B , rule 2
= A.1 + A.B + A’B, rule 12
= A + B(A +A’), rule 4 and 12
=A + B.1, rule 6
= A + B, rule 4

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Rule 12

(A + B) (A+C) = A + BC

Students to try this??

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 Commutative Laws
• The commutative law of addition for two
variables is written as A+B = B+A
• This law states that the order in which the
variables are ORed makes no difference.
• Remember, in Boolean algebra as applied to
logic circuits, addition and the OR operation
are the same.
• The law means the inputs of a gate are
interchangeable
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 Illustration

A Y= A+B B Y= B+A

B
≡ A

illustrates the commutative law as applied to the OR

gate and shows that it doesn't matter to which input
each variable is applied. (The symbol ≡ means
"equivalent to.").
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The commutative law of multiplication
for two variables is
• A.B = B.A
• This law states that the order in which the
variables are ANDed makes no difference.

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 Illustration
A Y=A.B B Y=B.A
B
≡ A

illustrates this law as applied to the AND gate

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 Associative Laws :
• The associative law of addition is written as
follows for three variables:
A + (B + C) = (A + B) + C
• This law states that when ORing more than
two variables, the result is the same
regardless of the grouping of the variables.
• A+(B.C)=(A+B).C NB/ Not equal to each other

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• The associative law of multiplication is written as
follows for three variables:
A(BC) = (AB)C
• This law states that it makes no difference in what
order the variables are grouped when ANDing more
than two variables.
• Any variables in the same function can be grouped
together and will not change the result
• The equation must ONLY consist of the same operator

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 Distributive Law
• The distributive law is written for three variables as
follows:
A.(B + C) = A.B + A.C
A+(B.C) = (A+B).(A+C)
• This law states that ORing two or more variables and
then ANDing the result with a single variable is
equivalent to ANDing the single variable with each of
the two or more variables and then ORing the
products.
• The distributive law also expresses the process of
factoring in which the common variable A is factored
out of the product terms
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BOOLEAN ANALYSIS OF LOGIC CIRCUITS
• Boolean algebra provides a concise way to
express the operation of a logic circuit formed
by a combination of logic gates so that the
output can be determined for various
combinations of input values
• To derive the Boolean expression for a given
logic circuit, begin at the leftmost inputs and
work toward the final output, writing the
expression for each gate.

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• For example circuit in Fig in the next slide, the
Boolean expression is determined as follows:
– The expression for the left-most AND gate with inputs
C and D is CD.
– The output of the left-most AND gate is one of the
inputs to the OR gate and B is the other input.
Therefore, the expression for the OR gate is B + CD.
– The output of the OR gate is one of the inputs to the
right-most AND gate and A is the other input.
– Therefore, the expression for this AND gate is A(B +
CD), which is the final output expression for the entire
circuit.

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 A logic circuit showing the development of
the Boolean expression for the output.

C
D CD

B B+CD

A(B+CD)
A

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 SIMPLIFICATION USING BOOLEAN
ALGEBRA
• A simplified Boolean expression uses the
fewest gates possible to implement a given
expression
• Example :
Using Boolean algebra techniques, simplify
this expression:
AB + A(B + C) + B(B + C)
AB+AB+AC+BB+BC
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 Solution
• Step 1:
Apply the distributive law to the second and third terms in the
expression, as follows: AB + AB + AC + BB + BC
• Step 2:
Apply rule 7 (BB = B) to the fourth term. AB + AB + AC + B + BC
• Step 3:
Apply rule 5 (AB + AB = AB) to the first two terms. AB + AC + B + BC
• Step 4:
Apply rule 10 (B + BC = B) to the last two terms.
AB + AC + B
• Step 5:
Apply rule 10 (AB + B = B) to the first and third terms.
B+AC
At this point the expression is simplified as much as possible

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LESSON 3

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 KARNAUGH MAP MINIMIZATION
• A Karnaugh map provides a systematic method for simplifying Boolean
expressions and, if properly used, will produce the simplest SOP or POS
expression possible, known as the minimum expression.
• As you have seen, the effectiveness of algebraic simplification depends on
your familiarity with all the laws, rules, and theorems of Boolean algebra
and on your ability to apply them.
• The Karnaugh map, on the other hand, provides a "cookbook" method for
simplification.
• A Karnaugh map is similar to a truth table because it presents all of the
possible values of input variables and the resulting output for each value.
Instead of being organized into columns and rows like a truth table, the
Karnaugh map is an array of cells in which each cell represents a binary
value of the input variables.

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• The cells are arranged in a way so that simplification of
a given expression is simply a matter of properly
grouping the cells.
• Karnaugh maps can be used for expressions with two,
three, four. and five variables.
• The number of cells in a Karnaugh map is equal to the
total number of possible input variable combinations as
is the number of rows in a truth table.
• For three variables, the number of cells is 23 = 8.
• For four variables, the number of cells is 24 = 16.

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 The 3-Variable Karnaugh Map
• The 3-variable Karnaugh map is an array of eight cells. as
shown in Table (a). In this case, A, B, and C are used for the
variables although other letters could be used.
• Binary values of A and B are along the left side (notice the
sequence) and the values of C are across the top.
• The value of a given cell is the binary values of A and B at
the left in the same row combined with the value of C at
the top in the same column. For example, the cell in the
upper left corner has a binary value of 000 and the cell in
the lower right corner has a binary value of 101.
• Table( b) shows the standard product terms that are
represented by each cell in the Karnaugh map.

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 0 1 0 1
AB C AB C
00 00 A’B’C’ A’B’C

A’BC’ A’BC
01 01
ABC’ ABC
11 11
AB’C’ AB’C
10 10

(a) (b)

A 3-variable Karnaugh map showing product terms

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 Cell Adjacency
• The cells in a Karnaugh map are arranged so that there
is only a single variable change between adjacent cells.
• Adjacency is defined by a single variable change.
• This ensures that physical neighbours in the array are
logical neighbours as well (i.e neighbouring bit patterns
are nearly the same, differing by only 1 bit)
• In the 3-variable map the 010 cell is adjacent to the
000 cell, the 011 cell, and the 110 cell. The 010 cell is
not adjacent to the 001 cell, the 111 cell, the 100 cell,
or the 101 cell.

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Adjacent cells on a Karnaugh map are those
that differ by only one variable.
Arrows point between adjacent cells

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• This one bit change applies at the edges too.
• So the cells in the same row on the left and
right edges of the array also differ by one bit.

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 Rules for the K-map
• Each cell with a 1 must be included in at least one group
• Try to form the largest possible groups
• Try to end with as few groups as possible
• Groups may be in sizes that are powers of 2 i.e 20 , 21,
22,23,24 ……
• Groups may be square or rectangular ONLY (including wrap
around at the grid edges). No diagonals or zigzags can be
used to form groups
• The larger the group is the more redundant inputs there
are
• Allow overlapping and wrap around
• Group may not include any cell containing a zero

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• Fold up the corners of the map below like it
is a handkerchief to make the four cells
physically adjacent. (WRAPAROUND)

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 Redundant inputs
• If there are two neighbouring 1’s in the grid, it
means that the input bit change between the
two cells has no effect on the output and thus
there is a redundancy.
– A group of 1 has no redundant input
– A group of 2 has 1 redundant input
– A group of 4 has 2 redundant inputs
– A group of 8 has 3 redundant inputs
– A group of 16 has 4 redundant inputs

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 Looping
• The expression for the output can be simplified by
properly combining those squares in the k-map that
contain 1.
• The process of combining these 1’s is called looping.
• Looping a pair of adjacent 1’s in a k-map eliminates the
variable that appears in complemented and
uncomplemented form
• When a variable appears in both complemented and
uncomplemented form within a loop, that variable is
eliminated from the expression.
• Variables that are the same for all squares of the loop
must appear in the final expression
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The steps below are followed in using the K-map
method for simplifying a Boolean expression:
• Step 1 Construct the K map and place 1s in those
squares corresponding to the 1s in the truth table.
Place 0s in the other squares.
• Step 2 Examine the map for adjacent 1s and loop
those 1s that are not adjacent to any other 1s.
These are called isolated 1s.
• Step 3 Next, look for those 1s that are adjacent to
only one other 1. Loop any pair containing such a 1.

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• Step 4 Loop any octet even if it contains some 1s
that have already been looped.
• Step 5 Loop any quad that contains one or more
1s that have not already been looped, making
sure to use the minimum number of loops.
• Step 6 Loop any pairs necessary to include any 1s
that have not yet been looped, making sure to
use the minimum number of loops.
• Step 7 Form the OR sum of all the terms
generated by each loop.

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 Example
• We will assume that the map was obtained
from a truth table

AB CD 00 01 11 10 A’B’CD’ (No redundancy-

ALL inputs included)
00 0 0 0 1

0 1 1 0
01
0 1 1 0 BD (2 redundant
11 inputs- A & C)
0 0 1 0
10 ACD (1 redundant input-B)

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X = A’B’CD’ + ACD + BD

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Use a K map to simplify y = C’(A’ B’ D’ + D) + AB’C + D’

Solution
•Multiply out the first term to get y = A’ B’ C’ D’ + C’D +
AB’C + D which is now in SOP form.
•For the term A’ B’ C’ D’ , simply put a 1 in the A’ B’ C’ D’
square of the K map (Figure 4-17).
•For the term C’D, place a 1 in all squares with C’D in their
labels, that is A’ B’ C’D, ABC’D, A’BC’D, A B’ C’D,

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• For the AB’C term, place a 1 in all squares that have
AB’C in their labels, that is A B’ C D’, A B’ C D
• For the D’ term, place a 1 in all squares that have a
D’ in their labels, that is, all squares in the leftmost
and rightmost columns.
• The remaining cell put zeros

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C’

D’
AB CD 00 01 11 10
00 1 1 0 1

1 1 0 1
01
AB’
1 1 0 1
11
1 1 1 1
10 Y=AB’+ C’+ D’

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Converting a Boolean Function From Truth
Table to SOP Algebraic Equation

A B C Output (X)
0 0 0 0
0 0 1 0
0 1 0 0 Express the boolean
0 1 1 1 expression for X in
1 0 0 0 the following truth
1 0 1 1 table?
1 1 0 1
1 1 1 1

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• Write a Boolean product expression for each row where the output column equals 1
• In simple terms, the output is true (or high) if any of the following statements are
true:
– B and C are true, A is NOT true..
– A and C are true, B is NOT true.
– A and B are true. C is NOT true.
– A,B and C are true
Using the chart in the example above, the Boolean expressions would be:
A'BC, AB’C, ABC’ ABC
• Join the product expressions by adding them with a + operator. Continuing the
example, the Boolean equation would be
OUTPUT (X) = A'BC + AB’C + ABC’ + ABC

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 K-MAP
• Consider the expression Z=f(A,B)=A’B’ +
AB’ + A’B plotted on the Karnaugh map:

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• Pairs of 1's are grouped as shown above, and the simplified
answer is obtained by using the following steps:
Note that two groups can be formed for the example given
above, bearing in mind that the largest rectangular clusters
that can be made consist of two 1s. Notice that a 1 can
belong to more than one group.

• The first group labelled I, consists of two 1s which

correspond to A = 0, B = 0 and A = 1, B = 0. Put in another
way, all squares in this example that correspond to the area
of the map where B = 0 contains 1s, independent of the
value of A. So when B = 0 the output is 1. The expression of
the output will contain the term B’

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• For group labelled II corresponds to the area of
the map where A = 0. The group can therefore
be defined as A’. This implies that when A = 0
the output is 1. The output is therefore 1
whenever B = 0 and A = 0
• Hence the simplified answer is
Z=A’+B’

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• Minimise the following problems using the
Karnaugh maps method

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• The minimised result obtained is

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Lesson 4

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COMBINATIONAL LOGIC CIRCUITS
• Unlike sequential logic circuits whose outputs are
dependant on both their present input and
previous output state giving them some form of
memory, the outputs of combinational logic
circuits are only determined by the logical
function of their current input state Logic “0” or
logic “1” at any instant in time as they have no
feedback and any change to the signals being
applied to their inputs will immediately have an
effect on the output

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• Combinational circuits have no memory,
timing (clocks) or feedback loops
• Examples of Combinational circuits:
– Decoder, Encoder, Multiplexer, De-multiplexer,
Adders, subtructors and comparator
• Examples of Sequential circuits:
– Flip flops and latches

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 DECODERS
• A decoder is a logic circuit that accepts a set of inputs
that represents a binary number and activates only the
output that corresponds to that input number.
• In other words, a decoder circuit looks at its inputs,
determines which binary number is present there, and
activates the one output that corresponds to that
number; all other outputs remain inactive.
• It is a combinational circuit that converts N bits of
binary information of input lines to a maximum of 2N
unique output lines.

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• In its general form, a decoder has N input lines to
handle N bits and form one to 2 N output lines to
indicate the presence of one or more N-bit
combinations
• The basic binary function
• An AND gate can be used as the basic decoding
element because it produces a HIGH output only
when all inputs are HIGH

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 General Decoder Diagram

A0
O0
N inputs A1 DECODER
O1

A2 O2
M outputs

AN-1 OM-1
Only one output
input
is HIGH for each
codes
input code
# There are 2N possible input combinations, from A0 to AN1.
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• Because each of the N inputs can be 0 or 1, there 2N are
possible input combinations or codes. For each of these
input combinations, only one of the M outputs will be
active HIGH (1); all the other outputs are LOW (0).
• Many decoders are designed to produce active-LOW
outputs, where only the selected output is LOW while all
others are HIGH. This situation is indicated by the presence
of small circles on the output lines in the decoder diagram.
• Note that for a given input code, the only output that is
active (HIGH) is the one corresponding to the decimal
equivalent of the binary input code (e.g., output O6 goes
HIGH only when CBA = 1102 = 610).

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• Some decoders do not utilize all of the 2N
possible input codes but only certain ones. For
example, a BCD-to-decimal decoder has a
four-bit input code and ten output lines that
correspond to the ten BCD code groups 0000
through 1001. Decoders of this type are often
designed so that if any of the unused codes
are applied to the input, none of the outputs
will be activated.
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• Usually decoders are designed as an N to M
line decoder where N= input lines and M=
output lines

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 2 to 4 line Decoder (1 of 4)

A0
O0 A0 O0
A1
A1
O1 O1

O2 O2

O3 O3
EN EN

(a)Logic symbol for active HIGH

(b)Logic symbol for active LOW

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• If an active-LOW output (74138, one of the output will
low and the rest will be high) is required for each decoded
number, the entire decoder can be implemented with
• NAND gates
• Inverters

• If an active-HIGH output (74139, one of the output will

high and the rest will be low) is required for each decoded
number, the entire decoder can be implemented with
• AND gates
• Inverters

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 ENABLE Inputs
• Some decoders have one or more ENABLE inputs that
are used to control the operation of the decoder. For
example, refer to the decoder in Figure (a) above and
visualize having a common ENABLE line connected to a
fourth input of each gate.
• With this ENABLE line held HIGH, the decoder will
function normally, and A0 A1 input code will determine
which output is HIGH.
• With ENABLE held LOW, however, all of the outputs
will be forced to the LOW state regardless of the levels
at the A0 A1 inputs. Thus, the decoder is enabled only if
ENABLE is HIGH.

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Truth table of 2-4 Decoder (Active High)

INPUTS ENABLE OUTPUTS

A1 A0 EN O3 O2 O1 O0
X X 0 0 0 0 0 O0= A1’AO’
0 0 1 0 0 0 1 O1= A1’AO
0 1 1 0 0 1 0 O2= A1AO ‘
1 0 1 0 1 0 0 O3= A1AO
1 1 1 1 0 0 0

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Implementation of 2 to 4 with Enabled input
A1
A0

O0

O
1

0
2

O3

EN
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• As we can see in the truth table for each input
combination, one output line is activated i.e. the
output line corresponding to the input combination
becomes 1 while other lines remain inactive(LOW).
• For example an input of 01 at the input will activate
line O1.
• Notice also that each output of the decoder is actually
a minterm resulting from certain combination of inputs
i.e. O0 = A1’AO’(Minterm Mo ) corresponds to output 00,
O1= A1’A0 ’(Minterm M1 ) corresponds to output 01

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 2-to-4-Line Decoder
(with Enable input)-Active LOW output

EN

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• The circuit operates with complemented outputs and a
complement enable input. The decoder is enabled
when EN is equal to 0.
• Only one output can be equal to 0 at any given time,
all other outputs are equal to 1.
• The output whose value is equal to 0 represents the
minterm selected by inputs A and B
• The circuit is disabled when EN is equal to 1

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 3-to-8 line Decoder
• In a 3-8 decoder, there are three inputs and eight
outputs.
• This decoder can be referred to in several ways. It can
be called a 3-line-to- 8-line decoder, because it has
three input lines and eight output lines.
• It could also be called a binary-octal decoder or
converters because it takes a three bit binary input
code and activates the one of the eight outputs
corresponding to that code.
• It is also referred to as a 1-of-8 decoder, because only
1 of the 8 outputs is activated at one time
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 BCD -to- Decimal decoders

•The BCD- to-decimal decoder converts each BCD code

into one of Ten Positionable decimal digit indications. It
is frequently referred as a 4-line -to- 10 line decoder
•The method of implementation is that only ten
decoding gates are required because the BCD code
represents only the ten decimal digits 0 through 9.
•Each of these decoding functions is implemented with
NAND gates to provide active -LOW outputs. If an
active HIGH output is required, AND gates are used for
decoding
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Logic diagram of BCD - decimal decoder
(Active LOW output)

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 Design a BCD - decimal decoder with active HIGH
outputs

• Solution:

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 Applications of Decoders
•Decoders are used in many types of applications. One example is in computers for
I/O selection as in previous slide

•Computer must communicate with a variety of external devices called peripherals

by sending and/or receiving data through what is known as input/output (I/O) ports

•Each I/O port has a number, called an address, which uniquely identifies it. When
the computer wants to communicate with a particular device, it issues the
appropriate address code for the I/O port to which that particular device is
connected . The binary port address is decoded and appropriate decoder output is
activated to enable the I/O port

•Binary data are transferred within the computer on a data bus, which is a set of
parallel lines

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 ENCODERS
• A digital circuit that performs the reverse operation of a decoder.
• An encoder has a number of input lines , ONLY one of which is
activated at a given time, and produce an N bit output code,
depending on which input is activated.
• For example for active HIGH input encoder, ONLY one input can be
logic 1 at any given time. All other inputs must be zeros (0’s)
• We can say that an encoder has 2N inputs and N output lines
• An encoder accepts an active LOW/HIGH level on one of its inputs
representing digits such as decimal or octal and converts it to a
coded output such as BCD or binary
• NB: Output lines generate the binary code corresponding to active
input

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 Block diagram for active high input
encoder

I0
O0
I1 O1
2N inputs only ENCODER
one HIGH at a I2 O2
time N outputs

IM-1 ON-1
Output lines generate the
binary code corresponding to
M= Number of inputs active input
N= Number of outputs
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 4 to 2 encoder (active HIGH inputs)
• Accepts 4 inputs lines and produce 2 bits output code
corresponding to the activated input

I0
O0 LSB
I1 O1 MSB
4 to 2
I2 ENCODER
I3

M=4, N=2
LOGIC SYMBOL

84
 Truth table
INPUTS OUTPUTS
I3 I2 I1 I0 O1 O0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

O 0 = I1 + I 3
O 1 = I2 + I 3

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 Logic circuit – 4 to 2

I I I I
3 2 1 0

O0 = I + I
1 23

O1 = I + I
2 3

Note that the I0 is not connected to the logic gates because the
encoder outputs will normally be at 0 0 when none of the inputs
I1 to I3 is HIGH
86
 An Octal to binary encoder (8 line to 3 line
encoder) with active HIGH inputs

• Accepts eight input lines and produce three

bit output code corresponding to the
activated input.
• It has eight inputs, one for each of the octal
digits and three outputs that generate the
corresponding binary number

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8 to 3 line encoder (active HIGH inputs)

I0
O0 LSB
I1 O1 MSB
8 to 3
I2 ENCODER O2

I7

M=8, N=3
LOGIC SYMBOL

88
 Truth table
INPUTS OUTPUTS
I7 I6 I5 I4 I3 I2 I1 I0 O2 O1 O0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
O0 = I1 + I3 + I5 + I7
O1 = I2 + I3 + I6 + I7
O2 = I4 + I5 + I6 + I7

89
 8 to 3 line encoder Logic circuit

I I I I I I I1 I0
7 6 5 4 3 2

O0 = I + I + I5 + I
1 3 7

O
1
= I + I + I6 + I
2 3 7

O2
= I + I + I + I
4 5 6 7

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• Limitations :
– I0 has no effect on the output
– Only one input can be activated at a given
time
• Application:
– Handling multiple devices requests
But, no simultaneous requests
• Establishing priorities solve the problem of
multiple requests (thus priority encoders)

91
 Priority Encoders
• In this type of encoder, a priority is assigned to
each input so that, when more than one input is
simultaneously active, the input with the highest
priority is encoded
• For example if I5 and I7 are active at the same time
line I5 will be ignored and I7 will be encoded
• Therefore, the output code will be 111
• You will note that with the previous encoders if
two or more inputs are active simultaneously, the
output produces undefined conditions.
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 Design 8 line to 3 line priority encoder with active high
inputs
TRUTH TABLE

INPUTS OUTPUT CODES

A7 A6 A5 A4 A3 A2 A1 A0 O2 O1 O0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 X 0 0 1
0 0 0 0 0 1 X X 0 1 0
0 0 0 0 1 X X X 0 1 1
0 0 0 1 X X X X 1 0 0
0 0 1 X X X X X 1 0 1
0 1 X X X X X X 1 1 0
1 X X X X X X X 1 1 1

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 Writing logic equation
• In order to write the logic equation for priority
encoder output, we first define 8 intermediate
variables HO to H7 such that Hi (0<i<7) is 1 iff Ai is
the highest priority input
– H7= A7
– H6 = A6A7’
– H5 = A5A6’A7’
– H4 = A4 A5’A6’A7’
– H3 = A3A4’ A5’A6’A7’
– H2 = A2A3’A4’ A5’A6’A7’
– H1 = A1A2’A3’A4’ A5’A6’A7’
– H0 = A0A1’A2’A3’A4’ A5’A6’A7’
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• Using these signals the equation for O0 to O2
outputs are similar to the ones of a simple
binary encoder
• O2 = H4 + H5 + H6 + H7
• O1 = H2 + H3 + H6 + H7
• O0 = H1 + H3 + H5 + H7

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 MULTIPLEXER (Data selector)
• Multiplexing means transmitting a large number of
information units over a smaller number of channels or
lines.
• Therefore, a digital multiplexer or a data selector is a logic
circuit that accepts several digital data inputs and selects
one of them at any given time to pass to the output.
• The routing of the desired data inputs to the output is
controlled by SELECT inputs often referred to as ADDRESS
inputs
• Normally, there are 2N input lines and N select lines whose
bit combinations determine which input is selected
• It has 1 output

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 Block diagram for MUX

2N (input source) 1

MUX
Output Destination

N (Select lines)

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 MUX types
 2-to-1 (1 select line) 2:1
 4-to-1 (2 select lines) 4:1
 8-to-1 (3 select lines) 8:1
 16-to-1 (4 select lines) 16:1

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 4-to-1 MUX
MP3 player
docking system

Laptop sound D0
card D1
D2 Y Surround sound
Digital satellite D3 system

Digital cable TV

(MSB)A B (LSB)

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 Truth table
A B OUTPUT (Y)
0 0 Y= D0 (MP3)
0 1 Y=D1 (Laptop)
1 0 Y=D2 (Satellite)
1 1 Y=D3 ( Cable TV)

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 Logic circuit
D0
1

D
1
2 Y

D2
3

D3
4

A B
SELECT LINES

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• In general Y= D0A’B’ + D1A’B + D2AB’ + D3AB
• With B =0 AND A=0, the above expression
becomes
Y= D0.1.1 + D1.1.0 + D2.0.1 + D3.0.0
=> Y = D0 thus gate 1 is enabled which indicates
that Y will be identical to the input Do which
in turn an be a fixed logic level or a time
varying logic signal
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 Multiplexer Applications
• Data selection
• Data routing
• Operation sequencing
• Parallel to serial conversion

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DEMULTIPLEXER (Data distributor)
• A multiplexer takes several inputs and transmits one of
them to the output.
• A demultiplexer performs the reverse operation. It takes a
single input and distribute it over several outputs.
• Demultiplexing is the process of receiving information from
one channel and distributing it over several channels
• It can also be defined as a device that receives information
on a single line and transmits this information on one of the
2N possible output lines.
• The selection of a single output line is controlled by bit
values of N select lines

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 Types of DEMUX
• 1- to – 2 ( 1 selet line) 1:2
• 1-to-4 (2 selet lines) 1:4
• 1-to-8 (3 selet lines) 1:8
• 1-to-16 (4 selet lines) 1:16

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 Logic symbol

DEMUX
1 2N
Input source Output (destination)

Select lines

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 1:4 DEMUX

B/W Laser printer

O0

O1 Fax machine

DEMUX
I
Computer O2

O3 Colour ink jet printer

Pen plotter

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 Truth table
SELECT LINES OUTPUT
A B Selected destination
0 0 B/W Laser printer
0 1 Fax machine
1 0 Colour ink jet printer
1 1 Pen plotter

SELECT LINES OUTPUT

A B O3 O2 O1 O0
0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0
1 1 I 0 0 0

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 Logic circuit
I O0

O1

O
2

O3

A B
SELECT LINES

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• Note the serial data (I) is applied to all the
AND gates
• The data select lines A and B enable only one
AND gate at a time.
• The serial data at the input will be passed by
the selected gate to one of the four outputs
O0 to O3

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 ADDERS
• Half Adder: is a combinational circuit that performs the addition of two bits, this
circuit needs two binary inputs and two binary outputs. E.g.
 1+0=1
 0+0=0
 0+1=1
 1 + 1 =10 (the most significant bit of this result is called the carry
• When the augend and addend numbers contain more significant digits, the carry
obtained from the addition of the bits is added to the next higher order pair of
significant bits. Here the addition involves three bits; the augend bit, addend bit
and the carry bit and produces a sum result as well as a carry
• A combinational circuit performing this type of addition operation is called a full
adder
 Full Adder is a combinational circuit that performs the addition of three bits
(two significant bits and previous carry).

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 Design of half adders

• Such a circuit has two inputs that represent the

two bits to be added and two outputs, with one
producing the SUM output and the other
producing the CARRY.
• The truth table in the next slide shows all
possible input combinations and the
corresponding outputs.

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 Truth table of a half adder
INPUTS OUTPUTS
X Y C (carry) S (sum)

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

SUM (S) = X’Y + Y’X

(Using sum of product form ------------1)
CARRY (C) = XY

113
• Where S is the sum and C is the carry
• We can also say that
S=X YY
(Using XOR and AND Gates)------------2
C = XY

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• From the truth table it can be seen that
outputs S and C functions are similar to
Exclusive OR and an AND gates functions
respectively

115
Implementation of half adder using equation 1

X Y

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Implementation of half adder using equation 2

X Y

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 Design of a full adder
• Full Adder is a combinational circuit that
performs the addition of three bits (two significant
bits and previous carry).
• It consists of three inputs and two outputs, two
inputs are the bits to be added (the addend and the
augend), the third input represents the carry from
the previous position (Cin).
• The S output is equal to 1 when only one input is
equal to 1 or when all three inputs are equal to 1
• The C out output has a carry 1 if two or three inputs
are equal to 1.
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 Truth table of a full adder
INPUTS OUTPUTS
X Y Cin S C out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

• The Karnaugh maps and the simplified

expression are shown in the next slide
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 Map for S Map for Cout
Cin Cin
XY 0 1 XY 0 1

00 0 1 00 0 0

1 0 0 1
01 01
0 1 1 1
11 11
1 0 0 1
10 10

S = X’YCin’ + X’Y’Cin + XYCin + XY’Cin’

Cout = XY + YCin + XCin (Sum of products ----------1)

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The logic diagrams for the full adder implemented in
sum-of-products form are the following:
X Y C
in

C
out

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• It can also be implemented using two half adders
and one OR gate (using XOR gates).
• S= X’YCin’ + X’Y’Cin+ XYCin + XY’Cin’
= X’YCin’ +XY’Cin’ + X’Y’Cin+ XYCin
=Cin’(X’Y + XY’) + Cin (X’Y’ + XY)
= Cin’(X Y) + Cin (X Y)----------------(i)
Let P = (X Y)
Threfore equation (i) beomes Cin’P + Cin P’ whih is
the same as
= Cin P but P = (X Y)
S = Cin X Y

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• C = XY + YCin + XCin
= XY + Cin (Y + X)
=XY + Cin (YX + YX’ + XY + XY’)
=XY + Cin (YX + YX’ + XY’)
= XY + Cin YX + Cin YX’ + Cin XY’
= XY(1 + Cin ) + Cin (YX’ +XY’)
= XY + Cin (X Y)

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 Logic diagram according to the
modified expressions
C X y
in

C
out

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• The full adder developed in the later diagram
has two 2 inputs AND gates, two 2 input EXOR
gates and one 2 input OR gates as compared
to the one developed from SOP.
• Also if compared with a half adder circuit, the
full adder circuit can be formed with two half
adders and one OR gate

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 SEQUENTIAL CIRCUITS

LATCHES AND FLIP FLOPS

• In the same way that gates are building blocks of
combinational circuits, latches and flip flops are the
building blocks of sequential circuits.
• Latches can be built from gates and flip flops can be
built from latches.
• Both latches and flip flops are circuit element whose
output depends not only on the current inputs, but
also on the previous inputs and outputs.
• The difference between a latch and a flip flop is that a
latch does not have a clock signal, where as a flip flop
always does.

SCO106 ELECTRONICS 126

• Digital systems can operate (transmit data) either asynchronously or
synchronously
• Asynchronous systems:- the output of logic circuit can change state
anytime one or more of the inputs change.
• Synchronous systems: - In this system, the exact times at which any
input can change state are determined by a signal commonly called
the clock
• Latches are asynchronous, which means that the output changes very
soon after the input changes.
• Most computers today, on the other hand, are synchronous, which
means that the outputs of all the sequential circuits change
simultaneously to the rhythm of a global clock signal.
• A flip-flop is a synchronous version of the latch.

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 Latches
• We will look at two types of latches
– SR Latch
– D Latch

S Q
_
R Q

SR NOR Latch Logic

symbol SIT 112_INTRODUCTION TO DIGITAL
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 SR NOR Latch (set reset latch)

R Q

S Q
_
R Q
Q'
S

Logic circuit Logic symbol

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 SR NAND Latch

S
Q S Q

R Q’

Q'
R
Logic circuit Logic symbol

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 SR composition
• It has two inputs S for set and R for reset
• Two outputs Q and Q’
• Two NOR/NAND gates are cross connected
with two outputs Q and Q’
• Q output always determines the state of the
latch

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 Truth table
S R Qn+1 S R Qn+1
0 0 Qn (No change) 0 0 Invalid
0 1 0 0 1 1
1 0 1 1 0 0
1 1 Invalid 1 1 Qn (No change)
SR NOR LATCH
SR NAND LATCH

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 SR Operation (NOR LATCH)
• If input S goes to a “1” while R stays “0” output
Q’ goes to a “0”. This LOW is coupled back to the
other NOR gate which will produce a 1 on output
Q because R is also “0”
• Recall that (0 + 0)’= 1
• The latch condition is represented by the normal
output Q. If Q = 1, the latch is said to be in SET
state.
• The input S is called the SET input which sets the
latch by active HIGH(1) input

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• When the input R goes to “1” while S stays
LOW (0), output Q goes to a “0”. This LOW (0)
is coupled back to the output of the other
NOR gate and with S=0, Q’ becomes a 1. If Q
=“0” the latch is said to be in RESET state. The
input R is called the RESET input and is active
HIGH (1). This input is also called the CLEAR
input

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• With both inputs equal to “0”, the output is
unpredictable since it can be a 1 or 0. Thus the
output state is predetermined by conditions
prior to the time when S and R both become
“0”. This output condition is specified in the
truth table as “No change”
• i.e. the latch will remember the value that has
been stored as long as S and R stay inactive.

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 SR Operation (NAND LATCH)
• The truth table shows that the NOR latch is
SET by applying a “0” to the S input, and
RESET by applying a “0” to the R input.
• When both inputs are “1” the latch is inactive
and the output remain unchanged.
• With both inputs zero the output becomes
unpredictable

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 D Latch
• This latch has two inputs and two outputs
• The two inputs are the D (data) and G
(enabled or gated)
• The two outputs are Q and Q’

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 D(data)
A
G(Gate/Enabled )
Q (output)

D Latch Logic circuit

D G Qn+1

0 0 Qn

0 1 0

1 0 Qn

1 1 1

D Latch truth table

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 D latch operation
• When the G input is equal to 1, gate A is open and gate B is
closed. Data at the D input is thus transferred to Q(output).
Therefore the Q output will follow the data input for the
time G=1
• When the enabled input G goes to 0, gate A closes and
gate B opens. The data at Q (output) is transferred through
gate B back to the output , retaining or locking the data in
the latch.
• NB: The output Q is only updated when G=1
• When the inputs D and G are both LOW (0) gate B will open
while gate A is closed implying that data at Q output is
transferred through gate B back to the output. Thus no
change will be realized at Q.

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 FLIP FLOPS
• Are synchronous bistable devices
• The output changes state at a specified point on
a triggering input called clock.
• They can change state at positive edge (rising
edge) or at the negative edge (falling edge) of the
clock signal
• Therefore we have positive edge triggered and
negative edge triggered flip flops.
• Examples of flip flops; SR, JK,D and T flip flops

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• The clock signal is generally a rectangular
pulse train or a square wave.
• The clock signal is distributed to all parts of
the system, and most (if not all) of the system
outputs can change state only when the clock
makes a transition

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 • When the clock goes from 0 to 1, this is
called the positive going transition (PGT)
• When the clock goes from 1 to 0, this is
called the negative going transition (NGT)
PGT NGT

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 Positive Edge triggered flip flops
• In this case we say the transition of data (data
capture time) is on the leading or positive
going edge of the clock.
• This means that the flip flop can change state
only when the signal applied to its clock input
makes a transition from 0 to 1

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 Logic symbol for positive edge
triggered flip flop

Q
Control inputs

Clock CLK

Q’

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 Positive Edge triggered SR flip flops
• In this case a third input is added to the SR flip
flop called the clock (CLK, CK, CP)
• A triangle identifies the clock input and
indicates the edge triggering.
• A triangle without a bubble indicates positive
triggering and with a bubble indicates
negative triggering

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Truth table and Logic symbol for Positive
Edge triggered SR flip flops
S R CLK Qn+1
S Q
X X 0 Qn
X X 1 Qn
CLK 0 0 Qn
0 1 0
R Q’ 1 0 1
1 1 invalid

Logic symbol Truth table

NB: The arrows on the truth table indicate the positive

triggering

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 Logic circuit for positive edge
triggered SR FF
S SET' Q
I II

Edge detector

CLK
RESET' IV Q'
R III
Control Gates SR NAND latch

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 Operation of Positive Edge triggered SR
flip flops
• When the clock input is “0” NAND gate I and III are closed and their outputs
stay HIGH. The input to the latch section gates II and IV are active LOW. I.e.
the HIGH outputs from gates I and III prevent the data from being updated in
the latch section thus the data stored in the latch section remain unchanged
• On the positive transition of the clock pulse, the edge detector routes a
narrow pulse spike to the control gates. The control gates are temporarily
opened to SET or RESET the latch. With S=1 and R = 0, the output of gate I
=“0” while the output of gate III = 1. These outputs cause the latch to SET (Q
=1)
• If the latch was SET prior to the clock pulse it will remain in SET state .
However, if S=“0” and R =“1” during the leading edge of the clock pulse, the
output of gate I stays HIGH (1) and the output of gate III goes LOW (0). This
condition causes the latch to RESET (Q=0)

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 D FLIP FLOPS
• The D type flip flop is similar to SR edge
triggered flip flop except for the inverter
between the S and R inputs as shown in the
logic circuit in the next slide.
D Q

CLK

Q’

Logic symbol

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 D flip flop logic circuit

D SET' Q
I II

Edge detector

CLK
RESET' IV Q'
III

Control Gates SR NAND latch

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 Operation of D flip flop
• When the clock changes from a 0 to 1 the
output Q is updated with data on the D input
• If the clock input remains 0 the output Q can
not be updated from the data on the D input
• With D=0 and clock pulse applied Q =0 and
the flip flop is in the RESET state.
• With D=1 and the clock pulse applied Q= 1
and the flip flop is in the SET state
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Truth table for D flip flop
D CLK Qn+1
X 0 Qn
X 1 Qn
0 0
1 1

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 JK FLIP FLOP
• The difference between SR and JK is that the
JK to not have an invalid state. When J and K
are both HIGH the output of the flip flop
toggles every time a clock pulse is applied.
• The toggling is obtained by cross coupling the
output Q and Q’ to input NAND gates

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 Logic circuit for JK

SET' Q
J I
II

Edge detector

CLK
RESET' IV Q'
K III
Control Gates SR NAND latch

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 Truth table for JK
J K CLK Qn+1 J Q
X X 0 Qn
X X 1 Qn
CLK
0 0 Qn
0 1 0
K Q’
1 0 1
1 1 Toggle

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 JK Operation
• Let us examine the toggle condition
– Assume that J=K=1 and that Q is in the LOW state
when a clock pulse occurs. With Q =0 and Q’ =1,
NAND gate I will steer a CLK to the SET’ input of
the NAND latch to produce Q= 1.
– If we assume that Q is HIGH when the CLK pulse
occurs, NAND gate III will steer CLK pulse to the
RESET’ input of the latch to produce Q =0. Thus Q
always ends up in the opposite state (toggles)

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 NEGATIVE EDGE TRIGGERED FLIP
FLOPS
• Same operation as positive edge triggered,
the only difference is that the output changes
state when the clock is on falling edge.
• Another difference is on the logic symbol
because the clock will have a triangle with a
bubble as shown S Q

CLK

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ELECTRONICS
 Truth tables for Negative Edge
triggered FFs
J K CLK Qn+1 D CLK Qn+1 S R CLK Qn+1
X X 0 Qn X 0 Qn X X 0 Qn
X X 1 Qn X 1 Qn X X 1 Qn
0 0 Qn 0 0 0 0 Qn
0 1 0 1 1 0 1 0
1 0 1 1 0 1
1 1 Toggle 1 1 invalid

In the truth table you can use or to represent negative edge triggering

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