CHAPTER -3

CENTRAL PROCESSING UNIT

CHAPTER Outline :
 Introduction

 General Register Organization

 Stack Organization

 Instruction Formats

 Addressing Modes

 Reduced Instruction Set Computer (RISC) and Complex Instruction Set

(CISC)
 CPU ARCHITECTURE
 The type of internal storage in the CPU is the most basic
differentiation. The majors are a stack, an accumulator, or a set
of registers.
● Single Accumulator Architecture
♦ Contains special purpose registers
♦ Hardwired Control unit for common bus system

● General Register Architecture

♦ Contains many general purpose regeisters
♦ Microprogrammed Control unit for common bus system

● Stack Architecture

2 / 44
 1. Single Accumulator
Architecture
T0: AR PC (S S S =010, T0=1)
0 1 2

T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)

I. * Result usually goes to the T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I 
IR(15)
Accumulator T1 S2
T0 Bus
II. *Accumulator has to be saved to S1
S0
memory quite often Memory
unit 7
 Address
-Hardwired Control unit used - Read
CU is made up of sequential and AR 1
combinational circuits to generate
LD
the control signals PC 2
INR
IR 5
LD Clock
Accumulator Architecture Common3 bus
 General Register Organization
Inpu
R1
2. General R2
Register R3
Architecture R4
-Registers hold R5
operands thus reduce
memory traffic R6
R7
Microprogrammed
Control –
A control memory on LD SELA MUX MUX
the processor contains SELB
microprograms that 3x8 A B
activate the necessary Decoder
control signals
OPR
ALU
SELD

4 / 44
 Microprogrammed Control unit
 Control Memory
● Contains sequences of microoperations, and stored in Read-only
memory (ROM).

 Control signals
● Group of bits used to select paths in multiplexers, decoders, arithmetic
logic units

 Control word
● There are 14 binary selection inputs in the unit, and their combined
value specifies the control word.
● It consists of four fields, SELA(3bits)- source A, SELB(3bits)-source
B, SELD(3bits) – destination and OPR(5bits) – ALU operation
selector.

5
 OPERATION OF CONTROL UNIT
The control unit directs the information flow through ALU by:
- Selecting various Components in the system
- Selecting the Function of ALU
[1] MUX A selector (SELA): BUS A  R2
Example: R1 <- R2 + R3 [2] MUX B selector (SELB): BUS B  R3
[3] ALU operation selector (OPR): ALU to ADD
[4] Decoder destination selector (SELD): R1  Out
Bus
3 3 3 5
Control Word SELA SELB SELD OPR
Binary
Code SELA SELB SELD
000 Input Input None
001 R1 R1 R1
Encoding of register selection fields 010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7
6
 ALU CONTROL
OPR
Encoding of ALU operations Select Operation Symbol
00000 Transfer A TSFA
00001 Increment A INCA
00010 ADD A + B ADD
00101 Subtract A - B SUB
00110 Decrement A DECA
01000 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA
Examples of ALU Microoperations
Symbolic Designation
Microoperation SELA SELB SELD OPR Control Word
R1  R2 - R3 R2 R3 R1 SUB 010 011 001 00101
R4  R4  R5 R4 R5 R4 OR 100 101 100 01010
R6  R6 + 1 R6 - R6 INCA 110 000 110 00001
R7  R1 R1 - R7 TSFA 001 000 111 00000
Output  R2 R2 - None TSFA 010 000 000 00000
Output  Input Input - None TSFA 000 000 000 00000
R4  shl R4 R4 - R4 SHLA 100 000 100 11000
R5  0 R5 R5 R5 XOR 101 101 101 01100
7
 General Register Organization
Input
OPR Operation R1

00000 Transfer A R2
R3
00001 Increment A R4
00010 Add A + B R5
00101 Subtract A − B R6

00110 Decrement A R7

01000 AND A and B LD SELA MUX MUX SELB

01010 OR A and B
3x8 A B
01100 XOR A and B Decoder
01110 Complement A OPR
ALU
10000 Shift right A SELD

11000 Shift left A

Examples: Microoperation SELA SELB SELD OPR

R1 ← R2 − R3 010 011 001 00101
R4 ← SHL R4 100 000 100 11000
8 / 44
Exercise - 1
Specify the control word that must be applied to the
processor of Fig. above to implement the following
microoperations.
a. R1 ← R2 + R3
b. R4 ← R4
c. R5 ← R5 – 1
d. R6 ← shl R1
e. R7 ← input

9 / 44
10 / 44
 Stack Organization
 A stack is a storage device that stores information in such a
manner that the item stored last is the first item retrieved-LIFO.
 The stack in digital computers is essentially a memory unit in
the cpu.
 A register that holds the address for the stack is called stack
pointer, holds top of stack address.
 There are two operations in stack data insertion – push and data
deletion – pop.

11 / 44
 Stack Organization
 LIFO Current
Last In First Out Top of Stack
TOS 0
1
2
3
4
5
SP 6 0 1 2 3
7 0 0 5 5
FULL EMPTY 8 0 0 0 8
9 0 0 2 5
Stack Bottom 10 0 0 1 5
Stack
12 / 44
 Stack Organization
 PUSH Current 1 6 9 0
SP ← SP – 1 Top of Stack
TOS 0
M[SP] ← DR 1
2
If (SP = 0) then (FULL ← 1)
3
EMPTY ← 0 4
5 1 6 9 0
SP 6 0 1 2 3
7 0 0 5 5
FULL EMPTY 8 0 0 0 8
9 0 0 2 5
Stack Bottom 10 0 0 1 5
Stack
13 / 44
 Stack Organization
 POP Current
DR ← M[SP] Top of Stack
TOS 0
SP ← SP + 1 1
2
If (SP = 11) then (EMPTY ← 1)
3
FULL ← 0 4
5 1 6 9 0
SP 6 0 1 2 3
7 0 0 5 5
FULL EMPTY 8 0 0 0 8
9 0 0 2 5
Stack Bottom 10 0 0 1 5
Stack
14 / 44
 Stack Organization
 Memory Stack
● PUSH PC 0
1
SP ← SP – 1 2

M[SP] ← DR
AR 100
● POP
101
DR ← M[SP] 102

SP ← SP + 1
200
SP 201
202

15 / 44
 Exercise - 2
 Let SP = 000000 in the stack of figure below. How many items
are there in the if:
A. FULL = 1 and EMTY = 0?
B. FULL = 0 and EMTY = 1?

16 / 44
 8.5
 (a) Stack full with 64 items.
 (b) stack empty

17 / 44
 Classifying Computer or Instruction Set
Architectures
 The type of internal storage in the CPU is the most basic
differentiation. The major choices are a stack, an
accumulator, or a set of registers.
– Stack Computer Architecture
– AC Computer Architecture
– General Purpose Register Computer Architecture

Input Bus Input Bus

General Other
Stack
ALU
ALU
AC Registers ALU
Purpose Registers
Registers

Stack Architecture Output Bus Output Bus

AC Architecture
GPR Architecture
Operand Locations in Four ISA Classes
GPR
 Code Sequence C = A + B
for Four Instruction Sets
Stack Accumulator Register Register (load-
(register-memory) store)
Push A Load A MOV R1, A MOV R1,A
Push B Add B Add R1, B MOV R2, B
Add Store C MOV C, R1 Add R3, R1, R2
Pop C MOV C, R3

memory memory
acc = acc + mem[C] R1 = R1 + mem[C] R3 = R1 + R2
Instruction Formats – number of addresses
 The number of address fields in the instruction format
depends on the internal organization of CPU
♦ Three-Address Instructions
– ADD R1, R2, R3 R1 ← R2 + R3
♦ Two-Address Instructions
– ADD R1, R2 R1 ← R1 + R2
♦ One-Address Instructions
– ADD M AC ← AC + M[AR]
♦ Zero-Address Instructions
– ADD TOS ← TOS + (TOS – 1)

Opcode Operand(s) or Address(es)

21 / 44
 Instruction Formats

Example: Evaluate X= (A+B)  (C+D)

 Three-Address
1. ADD R1, A, B ; R1 ← M[A] + M[B]
2. ADD R2, C, D ; R2 ← M[C] + M[D]
3. MUL X, R1, R2 ; M[X] ← R1  R2

22 / 44
 Instruction Formats

Example: Evaluate X= (A+B)  (C+D)

 Two-Address
1. MOV R1, A ; R1 ← M[A]
2. ADD R1, B ; R1 ← R1 + M[B]
3. MOV R2, C ; R2 ← M[C]
4. ADD R2, D ; R2 ← R2 + M[D]
5. MUL R1, R2 ; R1 ← R1  R2
6. MOV X, R1 ; M[X] ← R1

23 / 44
 Instruction Formats

Example: Evaluate X= (A+B)  (C+D)

 One-Address
1. LOAD A ; AC ← M[A]
2. ADD B ; AC ← AC + M[B]
3. STORE T ; M[T] ← AC
4. LOAD C ; AC ← M[C]
5. ADD D ; AC ← AC + M[D]
6. MUL T ; AC ← AC  M[T]
7. STORE X ; M[X] ← AC
24 / 44
 Instruction Formats
Example: Evaluate X= (A+B)  (C+D)
 Zero-Address
1. PUSH A ; TOS ← A
2. PUSH B ; TOS ← B
3. ADD ; TOS ← (A + B)
4. PUSH C ; TOS ← C
5. PUSH D ; TOS ← D
6. ADD ; TOS ← (C + D)
7. MUL ; TOS ← (C+D)(A+B)
8. POP X ; M[X] ← TOS
25 / 44
 Lecture 3.2 Addressing Modes

26 / 44
 Addressing Modes

Opcode Mode ...

 Implied
● AC is implied in “ADD M[AR]” in “One-Address”
instr.
● TOS is implied in “ADD” in “Zero-Address” instr.

 Immediate
● The use of a constant in “MOV R1, 5”, i.e. R1 ← 5

 Register
● Indicate which register holds the operand

27 / 44
 Addressing Modes
 Register Indirect
● Indicate the register that holds the number of the
register that holds the operand
R1
MOV R1, (R2)

 Autoincrement / Autodecrement R2 = 3

● Access & update in 1 instr. R3 = 5

 Direct Address
● Use the given address to access a memory location

28 / 44
 Addressing Modes
 Indirect Address
● Indicate the memory location that holds the address of
the memory location that holds the data

AR = 101

100
101 0 1 0 4
102
103
104 1 1 0 A

29 / 44
 Addressing Modes
 Relative Address
● EA = PC + Relative Addr 0
1
PC = 2 2

100
AR = 100
101
102 1 1 0 A
Could be Positive 103
or Negative 104
(2’s Complement)

30 / 44
 Addressing Modes
 Indexed
● EA = Index Register + Relative Addr

Useful with XR = 2
“Autoincrement” or
“Autodecrement”
+

100
AR = 100
101
Could be Positive
or Negative 102 1 1 0 A
(2’s Complement) 103
104

31 / 44
 Addressing Modes
 Base Register
● EA = Base Register + Relative Addr

Could be Positive AR = 2
or Negative
(2’s Complement)
+

100 0 0 0 5
BR = 100
101 0 0 1 2
102 0 0 0 A
Usually points 103 0 1 0 7
to the beginning 104 0 0 5 9
of an array

32 / 44
 Types of Instructions
 Data Transfer Instructions
Name Mnemonic
Data value is
Load LD not modified
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP

 Data Manipulation Instructions

 Program Control Instructions
33 / 44
 Data Transfer Instructions

Mode Assembly Register Transfer

Direct address LD ADR AC ← M[ADR]
Indirect address LD @ADR AC ← M[M[ADR]]
Relative address LD $ADR AC ← M[PC+ADR]
Immediate operand LD #NBR AC ← NBR
Index addressing LD ADR(X) AC ← M[ADR+XR]
Register LD R1 AC ← R1
Register indirect LD (R1) AC ← M[R1]
Autoincrement LD (R1)+ AC ← M[R1], R1 ← R1+1

34 / 44
 Data Manipulation Instructions
Name Mnemonic
 Arithmetic Increment INC
Decrement DEC
 Logical & Bit Manipulation Add ADD
Subtract SUB
 Shift Multiply MUL
Divide DIV
Add with carry ADDC
Subtract with borrow SUBB
Name Mnemonic
Negate NEG
Clear CLR
Complement COM Name Mnemonic
AND AND Logical shift right SHR
OR OR Logical shift left SHL
Exclusive-OR XOR Arithmetic shift right SHRA
Clear carry CLRC Arithmetic shift left SHLA
Set carry SETC Rotate right ROR
Complement carry COMC Rotate left ROL
Enable interrupt EI Rotate right through carry RORC
Disable interrupt DI Rotate left through carry ROLC
35 / 44
 CISC
 Complex Instruction Set Computer
● Large number of instructions with a complicated ALU
● Some instructions perform specialized tasks and are
used infrequently
● Large variety of addressing modes
● Variable length instruction formats
● Instructions can manipulate operands in memory

36 / 44
 RISC
 Reduced Instruction Set Computer
● Relatively few instructions, hence simple ALU
● Relatively few addressing modes
● Memory access limited to “load” and “store”
● All operations done within “registers” of the CPU
● Fixed-length and easily decoded instruction format
● Single-cycle instruction execution
● Hardwired control unit

37 / 44