Unit 7

Computer Organisation and Architecture

 Chapter
Subtopics textbook
1Processor, Memory ( RAM and ROM) 32
2Role of Buses 32
3I/O Controller 32
4Von Neumann and Harvard Architecture and their comparison 32
5Program stored concepts ( FDE Cycle) 33
6 Control unit , ALU, clock and role of registers ( PC, MAR, MBR,CIR, ACC) 33
7How FDE cycle works 33
How processor performance can be improved, system clock , clock speed,
Buses/ word length, Cache memory and its impact on the processor
8 performance 33
9Role of interrupt and Interrupt Service Routine, Priorities 33
10Format of machine instruction set ( op code , operands) 34
11Addressing mode ( immediate and direct) 34
Machine instruction to solve problems( Arithmetic, Comparison and branching
12 and logical bitwise) 34
13barcode readers 35
14Laser scanners 35
15digital cameras 35
16 RFID 35
17 CCD 35
18 Laser printers 35
19Hard Disk ( magnetic ) 35
20 Optical disk 35
21SSD ( principle of operations, NAND flash memory) 35
The CPU
Components of the CPU
The CPU main components
• Control Unit
• Arithmetic-Logic Unit (ALU)
• A register is a fast
memory location in the
CPU itself
• Cache is located on the CPU –
it is slower to access than
registers but faster than RAM, it stores data that is frequently
accessed. It stores the data
which is frequently needed by the
processor
Memory( RAM and ROM )
RAM (RANDOM ACCESS MEMORY) R O M ( R E A D O N LY M E M O R Y )

1. It is volatile which means that data is lost 1. It is non-volatile which means that permanent data will
when the power is switched off remain even when the power is switched off

2. It is used to store data, files, or part of the 2. It is often used to store the start-up instructions when the
operating system that are currently in use computer is first switched on

3. Data on a ROM chip is read only which means this cannot be

3. This is read and write memory which changed.
means data can be changed in the memory

4. It usually has a storage capacity of a few 4. It usually has a storage capacity of only a few thousand
gigabytes bytes.

5. Made up of millions of memory locations

with unique addresses. Each cell contains
either data or instruction
 Buses are the group of parallel microscopic wires
that connect processor with :
• Input and output controller
Buses • Internal components of the processor ( registers)
• Processor with the memory ( RAM)
Control Bus
Address Bus and
Data bus
I/O Controller
• In addition to communication with memory, processor also communicates with the
input and output connected devices. This communication is through I/O controller
• External devices are connected via I/O port ( USB Port) e.g., printer plugged into
one of the port ( peripherals)
• Inside the computer, processor doesn’t communicate directly with the I/O device.
Instead, a device / interface is used which is called I / O controller .
• Controller consists of its own circuitry that handles the data flow between
processor and device. Every device has its own controller , a monitor controller, a
mouse controller, a keyboard controller.
• There is relative difference in the processor speed and the I/O device , therefore I/O
controller used to buffer data being sent between processor and device
• Peripheral : A device that communicate through I/ O controller, not directly
controlled by the processor

Reasons that why controller is used for communication between I/O hardware and processor are in red
font
 Harvard and Neumann
Architecture
Reason Why Harvard Architecture is used by the processor preferably in
embedded / control systems:
• Instruction and data can be accessed simultaneously as instructions and data
are stored in the separate memory whereas von Neumann uses combined
memory for both instructions and data.
• Avoid/reduce bottleneck of single data/address bus(es) // avoid/reduce
delays waiting for memory fetches;
• Being able to use exclusively ROM for instruction memory prevents the
program being modified/hacked;
• Instruction and data memory can have different word lengths;
• Different technologies can be used to implement instruction and data
memory;
•Different quantities of instruction and data memory means that address lengths
can differ between the two // memory address structures can differ;
•Harvard Architecture is widely used in embedded system ( mobile phones,
burglar alarms rather than general purpose PCs. These embedded devices use
Digital Signal Processing ( DSP). DSP take real world data such as audio or video
and then compress it for fast processing. Chip that is optimized for DSP uses low
power consumption which is ideal for embedded systems
Control Unit

The control unit coordinates and controls all of the activities taking place
within the CPU
• Breaks down processing into sequential steps fetching address,
data/instruction , decoding and manages execution
• It receives signals from the system clock
• It directs the timing and control of other parts of the CPU, much like the
conductor of an orchestra
 The system clock — also simply referred to as the clock —
generates regular clock pulses by emitting a signal that
continuously oscillates between a low (or '0') and a high (or
'1') state. The clock signal is used to synchronise the
operations of the processor components.
System Clock
A 'rising edge' is a change from a low (or '0') state to a high
(or '1') state. The opposite is called a 'falling edge'. The time
taken between two sequential rising edges is called
the clock period and it corresponds to one clock cycle.

Every operation of the processor typically requires a number

of clock cycles to complete; the number of cycles is specific
to each type of processor. For example, fetching data from
memory could require many clock cycles even though it
may be described as one operation.
ALU ( Arithmetic
Logic Unit)
The ALU is responsible for performing
arithmetic calculations and logical operations
that include:
• Addition, subtraction, multiplication, division
• Logical bitwise operations, such as AND, OR,
NOT, and XOR
• Comparisons between values, such as
greater than, less than, equal to
• Shifting binary patterns to the left or right
 • Instructions are loaded to primary
memory ( RAM/ IAS/ Main Memory)
Stored • Instructions are fetched from primary
program memory ( RAM) one by one to be
decoded and executed by the processor
Concept ( FDE Cycle).
Fetch Decode Execute

Stage What happens at this stage?

FETCH Instructions to be executed are fetched by the processor using buses from the RAM
and stored in registers in the processor

DECODE Instruction in CIR is decoded by the control unit to understand the instruction and
signals are sent to execute the instruction

Execute ALU executes the instructions if instruction is to perform arithmetic or logical or

comparison operation. I/O instructions are executed by the I/O devices
General Purpose
registers
Registers are locations of computer memory
within the processor that provide extremely
fast access. Registers should not be confused
with the addressable locations of main
memory.

General-purpose registers
•Having to access the main memory can slow
down the execution of instructions.
Therefore, the processor uses registers to
temporarily store and access the results of
operations. The ALU is connected to a set of
general-purpose registers that are used to
keep the results of the intermediate
calculations that are produced as part of a
larger computation
Dedicated registers
Unit 7

Fetch:
•Contents of Program Counter / PC transferred to Memory Address Register /MAR
•Address bus used to transfer this address to main memory
•Transfer of content uses the data bus
•Contents of addressed memory location loaded into the Memory Buffer Register /MBR
•Increment (contents of) Program Counter / PC A. at any part of fetch process after transferring
PC to MAR
•Increment Program Counter / PC and fetch simultaneously
•Contents of MBR copied to CIR
Decode:
•Decode instruction held by the (Current) Instruction Register / (C)IR
FDE Cycle •The control unit decodes the instruction
•Instruction split into opcode and operand
Execute:
•If necessary, data is fetched
•If necessary, data is stored in memory
•The opcode identifies the type of operation/instruction to be performed (by the
•processor)
•Result (maybe) stored in register/accumulator
•The operation (identified by the opcode) is performed by the processor. A. ALU
Status register updated
•If jump / branch required Program Counter/PC is updated
 (increase the) data bus width: Enables more bits (A. data) to be transferred between main memory and
the processor at one time (so fewer read/write operations needed);
(increase the) clock speed enables more instructions to be executed per unit of time/second. Clock
generates a signal that is used to synchronize the operation of the process and movement of the data
around the other components of the computer

How (increase the) amount of cache memory; cache memory is faster than main memory so the more that can
be stored in cache memory the less frequently the main memory needs to be accessed;

processor (increase the) word length; larger word size means that the processor can process more bits in one go;
Increase the width of address Bus: More Addressable locations are possible
performance (change the) type/ capacity of cache memory; some types of cache memory can be accessed faster; More
instructions/data can be stored in the cache; This increases the probability that a particular data

can be item/instruction is in the cache when fetched // this increases the probability of a cache hit // fewer
fetches from main memory will be required;

improved (increase the) number of general-purpose registers: more intermediate results/variables can be kept in
processor registers rather than in main memory;
Increase number of cores
the more cores a computer has, the more instructions it can execute at the same time. As a result, the
computer will perform more efficiently than computers with the same type of processor but fewer cores.
Note that having a quad-core instead of a dual-core processor (both running at the same speed) does not
mean that the amount instructions that can be processed in the same time frame will double. However,
the quad core will still achieve a significant improvement because data and instructions need to be fed to
the cores appropriately and so the computer system will need to spend time organising which cores
receive which data and instructions. Also, the efficiency of a multicore processor depends on the nature of
the required task, i.e. if it is possible to divide a computation into subtasks that can be processed in parallel
(one task per core at the same time). This is known as parallel processing, and it is only possible on
multicore systems
Why • To execute the instruction, processor may
have to fetch more instructions/ data from
instructions the memory, this will overwrite the
stored in CIR instruction in MBR
• This is the reason first instruction are stored
are processed to CIR and then decode and execution starts
and if instruction/ data execution is to fetch
but not in data/ instruction that will be fetched and will
be stored to MBR
MBR
Handling
of Interrupt by The processor can be interrupted for a number of reasons,
including:
the processor •A hardware device has signaled that it has data to
process
•A hardware device has completed a task that it was
Interrupt is the signal to the
processor to stop doing its asked to do
•A software process needs a service to be provided or OS
current job and service the
interrupt, Interrupt can be function to be performed
initiated by Software and •An allotted amount of time has expired, and an action
Hardware . The purpose of the needs to be performed
interrupts are to help the •A hardware failure has occurred and needs to be
processor to prioritize and addressed
execute multiple tasks
simultaneously.
Why content of registers are stored
before the interrupt is serviced:
Processor can return to the current
processing of the program after interrupt
is serviced.
Process of servicing an interrupt
Machine Instruction opcode and operand

Opcode: The bits used for the opcode are 6 including

addressing mode bit , this means 2 to the power of 6 ,
which is 64 instructions opcode are possible in these
bits
Addressing mode is either 0/1:
In direct addressing is 1, the value stored in the
operand is the address of the memory location which
contains the data to process.
In immediate addressing 0, the operand is the value ,
Watch this video to understand the concepts listed on right
mentioned with the #
LDA R1 #12 ( immediate addressing )
STO R1 15 ( direct addressing)
Operand is 10 bits that means, 2 to the power of 10
operands are possible in 10 bits
Two bits for addressing mode, there are more than two addressing
modes so there are situations where more bits are sued for
addressing
Machine Instruction set- 1
Data transfer and Arithmetic instruction Comparison and branching

LDR , loads memory address content to register

STR stores register value to the memory address
MOV is used for assignment statement, assign the operand ( value or register) to the register
• You must know how to write the machine instruction code for loops / selections
• You must know how to fill in the trace table for the provided machine code
Instructions set -2
Logical Operations Logical shift
 Logical AND of a register R0 is Value A, R1 can be used for
Finding operand with a number 1 can Value b
help to find if a number is even
Even and or odd
Machine code :

odd R0 is an 8-bit register that

holds a number.
AND R3, R0 #1
CMP R3 # 1
BNE JUMP
AND R3, R0, #1 MOV R2 , #69
Convert the below HLL code to B END
machine code JUMP:
IF IsEven(A) MOV R2, # 79
END:
THEN B = 69
HALT
ELSE B = 79
ENDIF
 • A light source / laser is shone at bar code // a bar code is illuminated
• (moving) mirror/prism moves light beam across bar code // user moves
reader across bar code // user moves the bar code across the reader;
Principle of • Light reflected back;

operation – • Black/white bands reflect different amounts of light // black reflects less
light // white reflects more light;

Barcode • Light sensor / photodiode / CCD (measures amount of reflected light);

• Light reflected converted into an electrical signal;
scanner • convert reflection to (binary) numbers / characters / ASCII
Check Digit:
The (12) data digits are passed through a function to calculate a check digit;
The result is compared against the check digit read in // check digit
compared to rest of bar code;
If they do not match an error is indicated;
If they match the bar code is accepted and processed;
Principle of operation of optical disk
Reading mechanism from disk
• (Low power beam of) laser / light is shone at disk
• Light is focused on spot on track
• (Some) light is reflected from disk
• Amount of light reflected back is measured // light sensor detects
reflection
• Disc spins at constant linear velocity
How data is represented
• Data is stored on one/spiral track
• Continuation of land/pit reflects light whereas transition between
land and pit scatters light. Land reflects light whereas pits scatter
light/do not reflect light or vice-versa
• Transition between land and pit indicates a 1 and continuation of
land/pit represents 0
 Print drum coated in (positive static) charge
Printer generates bitmap of page from the data
Laser beams shone / directed at / draws on print drum
Via rotating (octagonal) mirror
Laser is modulated (turned on & off)
Principle of Laser removes / neutralises / reverses electric charge on drum

operation – where image should be dark / black

Toner is given (positive) charge
Laser printer Charged drum picks up toner
For drum/laser mechanisms, one for each colour (cyan etc)
Toner transferred (from drum) to paper / paper rolled over drum (to
transfer toner)
Toner is fused / bonded / melted / stuck to paper (by heated rollers /
pressure) (must
be clear that toner is already on paper when it is fused, not still on
drum)
 - Light enters through the lens on to (an array of
sensors on) the sensor chip.
- Each sensor produces an electrical current/signal;
Principle of
operation of - The signal represents a pixel;
Digital
Camera - An (ADC) converts measurement of light intensity
into binary/digital data;
- (Colour) filter is applied to generate separate data
values for red, green and blue colour components;
- The pixels are recorded as a group / array;
Principle of
operations of
flatbed
scanner
Principle of
operations of RFID
• RFID (radio frequency identification) allows data to be
transmitted wirelessly over radio waves.
• There are two parts to an RFID system: a tag and a reader.
Use of radio signals means that the system does not
require a line of sight between the tag and the reader.
• RFID tags are made up of an antenna, for receiving and
transmitting the radio frequency signals, and a chip, which
processes the signals. Each tag has a unique identifier and
will often store some additional data in a non-volatile
memory cell.
• The RFID reader transmits an encoded radio signal to
interrogate the tag. The tag receives the message and
then responds with its identifier and any other stored data
(for example, a stock number or product ID). Readers can
process multiple tags at the same time as each has a
unique identifier.
 RFID
• The RFID tags could be read without moving the products to locate the
code
• RFID tags can be read from distance of up to 300 meters unlike barcodes
• No manual scanning of codes
• RFID tags can be read at faster rate
• RFID tags are less likely to be damaged in comparison to the barcodes.
• RFID can be read without line of sight
• RFID consists of small microchip transponder and antenna.
• Can be injected in the skin for the identification of the pets.
• Two types of RFID tags are used, active and passive. Active tags are larger
in size with battery, actively transmit the signal used in Salik. Active tags
transmit signals , used for tracking of objects.
• Radio waves emitted from the reader up to a meter away to provide
sufficient electromagnetic power to the card using its coiled antenna.
• Transponder in the car send the data to the reader nearby.
Solid State Drives (SSD)
Basic features:
• Solid-state disks use
non-volatile flash memory to store
information
• Very fast read/write speeds as it doesn’t
need to wait for a disk to spin to the
correct location and an arm to move
• No mechanical or moving parts meaning
these disks are very durable
• Floating gate and Control Gate transistors
matrix ( NAND Technology) are used to
store 0’s and 1s as the movement of
electrons in these transistors
 Advantages /disadvantages
of SSDs
• Advantages:
• Highly durable, no moving parts, very fast read/write speeds, no noisy fan or drive arm, faster start up times,
Compact in size,
• Disadvantages:
• More expensive than magnetic hard disks, similar storage capacity as magnetic disks
• Longevity and Endurance – SSD has limited of read and write operations – 20 GB in 3 years
• Uses:
• Higher end computers
• Laptops ( because SSD is light weight and compact)
• Smartphones and tablets
• Capacity:
• 100GB – 16TB
Flash memory/ SSD
• Low cost, portable, no moving parts, durable
• Use the same NAND Flash technology to store the data
• This makes them ideal for a range of offline devices:
• Cameras
• Mobile phones
• USB memory sticks
Hard disks
• Parts of a hard disk
Drive read/write head reads data
on the drive using electromagnets
Magnetic platter
contains data –
Hard disks may
contain more
than one platter
Actuator
moves the
read/write arm

Drive spindle rotates

Magnetic disks
Basic features:
• Disk contains concentric
circles called tracks
• Each track is divided
into sectors
• Disk heads mounted on
mechanical arms read
and write the data
• Data is stored on the
magnetised platter
Magnetic storage
• Advantages:
• Cheap, large storage capacities, relatively fast write speed
• Disadvantages:
• Lots of mechanical parts, durability an issue, sealed unit due
to disk head and platter precision. Large in size in comparison
to other Secondary storage with similar storage capacity
• Uses:
• Personal computers, storage of large quantities of data
• Capacity:
• 500GB - 12TB or greater
Practice Exam Questions

Machine Instruction practice

Unit 7 practice questions