Module-II

ARM Architecture

1
Department of EECE-19ECS431-EMBEDDED SYSTEMS 2
2
CISC vs RISC

Department of EECE-19ECS431-EMBEDDED SYSTEMS 3

3
 RISC Design policy
• The ARM core uses a RISC architecture.

• RISC is a design philosophy aimed at delivering simple

but powerful instructions that execute within a single
cycle at a high clock speed

• The RISC philosophy concentrates on reducing the

complexity of instructions performed by the hardware
because it is easier to provide greater flexibility and
intelligence in software rather than hardware.

• RISC design places greater demands on the compiler

Department of EECE-19ECS431-EMBEDDED SYSTEMS 4
4
RISC Design policy

CISC relies more on the hardware for instruction

functionality, and consequently the CISC instructions are
more complicated

Department of EECE-19ECS431-EMBEDDED SYSTEMS 5

5
RISC Design policy

The RISC philosophy is implemented with four major

design rules:

1. Instructions
2. Pipelines
3. Registers
4. Load-store architecture

Department of EECE-19ECS431-EMBEDDED SYSTEMS 6

6
RISC Design policy
1. Instructions:
• RISC processors have a reduced number of instruction
classes.
• These classes provide simple operations that can each
execute in a single cycle.
• The compiler synthesizes complicated operations by
combining several simple instructions.
• Each instruction is a fixed length to allow the pipeline to
fetch future instructions before decoding the current
instruction
• CISC processors the instructions are often of variable size
and take many cycles to execute.
Department of EECE-19ECS431-EMBEDDED SYSTEMS 7
7
RISC Design policy

2. Pipelines
• The processing of instructions is broken down into
smaller units that can be executed in parallel by
pipelines.

• Ideally the pipeline advances by one step on each

cycle for maximum throughput.

• Instructions can be decoded in one pipeline stage

Department of EECE-19ECS431-EMBEDDED SYSTEMS 8

8
RISC Design policy

2. Pipelines
• The processing of instructions is broken down into
smaller units that can be executed in parallel by
pipelines.

• Ideally the pipeline advances by one step on each

cycle for maximum throughput.

• Instructions can be decoded in one pipeline stage

Department of EECE-19ECS431-EMBEDDED SYSTEMS 9

9
RISC Design policy

3. Registers

• RISC machines have a large general-purpose

register set.
• Any register can contain either data or an address.
• Registers act as the fast local memory store for all
data processing operations.
• In contrast, CISC processors have dedicated
registers for specific purposes.

Department of EECE-19ECS431-EMBEDDED SYSTEMS 10

10
RISC Design policy

4. Load-store architecture
• The processor operates on data held in registers.
• Separate load and store instructions transfer data
between the register bank and external memory.
• Memory accesses are costly, so separating memory
accesses from data processing provides an advantage
because you can use data items held in the register
bank multiple times without needing multiple
memory accesses.
• In contrast, with a CISC design the data processing
operations can act on memory directly.

Department of EECE-19ECS431-EMBEDDED SYSTEMS 11

11
The ARM Design Philosophy

Number of physical features

1. Portable embedded systems require some form of battery power.

The ARM processor has been specifically designed to be small

to reduce power consumption and extend battery operation—
Mobile phones and personal digital assistants (PDAs).

2. High code density is another major requirement since

embedded systems have limited memory due to cost and/or
physical size restrictions.

High code density is useful for applications that have limited on-
board memory, such as mobile phones and mass storage devices.

Department of EECE-19ECS431-EMBEDDED SYSTEMS 12

12
The ARM Design Philosophy
3. Embedded systems are price sensitive and use slow
and low-cost memory devices.
For high-volume applications like digital cameras, every
cent must be accounted for in the design.

4. Important requirement is to reduce the area of the die

taken up by the embedded processor
The smaller the area used by the embedded processor, the
more available space for specialized peripherals.

Department of EECE-19ECS431-EMBEDDED SYSTEMS 13

13
The ARM Design Philosophy
Classification of embedded system
5. ARM has incorporated hardware debug technology
within the processor so that software engineers can view
what is happening while the processor is executing code.

Software engineers can resolve issues faster, which has a

direct effect on the time to market and reduces overall
development costs.

Department of EECE-19ECS431-EMBEDDED SYSTEMS 14

The General Purpose Registers (GPR’s) in the ARM

• CPUs use registers to store data temporarily.

• To program in Assembly language, we must understand the
registers and architecture of a given CPU and the role they
play in processing data.

• That information could be a byte of data to be processed, or

an address pointing to the data to be fetched
The 32 bits of a register are shown below

Department of EECE-19ECS431-EMBEDDED SYSTEMS 15

The General-Purpose Registers (GPR’s) in the
ARM
Classification of embedded system
• The 32-bit data size of the ARM is often referred as word
• In ARM there are 13 general purpose registers. They are
R0–R12

Department of EECE-19ECS431-EMBEDDED SYSTEMS 16

The General Purpose Registers (GPR’s) in the
ARM
Classification of embedded system

Department of EECE-19ECS431-EMBEDDED SYSTEMS 17

The General Purpose Registers (GPR’s) in the
ARM
Classification of embedded system
• The general-purpose registers in ARM are the same as the
accumulator in other Microprocessors.
• They can be used by all arithmetic and logic instructions.
• The ARM core has three special function registers of R13, R14, and
R15.

ARM Instruction Format

• The ARM CPU uses the tri-part instruction format for most
instructions. One of the
instruction destination,source1,source2
• Depending on the instruction the source2 can be a register,
immediate (constant) value, or memory. The destination is often a
register or read/write memory.
Department of EECE-19ECS431-EMBEDDED SYSTEMS 18
Contd…
Classification of embedded system
MOV instruction:
• Simply stated, the MOV instruction copies data into register or from
register to register. It has the following formats:
• MOV Rn,Op2 ;load Rn register with Op2 (Operand2). Op2 can be
immediate
• Op2 can be an immediate (constant) number #K which is an 8-bit
value that can be 0–255 in decimal, (00–FF in hex). Op2 can also be
a register Rm. Rn or Rm are any of the registers R0 to R15. If we
see the word “immediate”, we are dealing with a constant value that
must be provided right there with the instruction. Notice the #
before immediate values.
• The following instruction loads the R2 register with a value of 0x25
(25 in hex).
• MOV R2,#0x25 ;load R2 with 0x25 (R2 = 0x25)
Department of EECE-19ECS431-EMBEDDED SYSTEMS 19
Contd…
Classification of embedded system
MOV instruction:
• MOV R1,#0x87 ;copy 0x87 into R1 (R1 = 0x87)
• The following instruction loads R5 with the value
of R7.
• MOV R5,R7 ;copy contents of R7 into R5 (R5 =
R7)

Department of EECE-19ECS431-EMBEDDED SYSTEMS 20

Contd…
Classification of embedded system
MOV instruction:
• When programming the registers of the ARM microcontroller with
an immediate value, the following points should be noted:
1. We put # in front of every immediate value.
2. If we want to present a number in hex, we put a 0x in front of it. If
we put nothing in front of a number, it is in decimal. For example, in
“MOV R1,#50”, R1 is loaded with 50 in decimal, whereas in “MOV
R1,#0x50”, R1 is loaded with 50 in hex ( 80 in decimal).
3. If values 0 to FF are moved into a 32-bit register, the rest of the bits
are assumed to be all zeros. For example, in “MOV R1,#0x5” the
result will be R1=0x00000005; that is,
R1=00000000000000000000000000000101 in binary.
4. Moving an immediate value larger than 255 (FF in hex) into the
register will cause an error.
Department of EECE-19ECS431-EMBEDDED SYSTEMS 21
Contd…
Classification of embedded system
MOV instruction:
• Note!
• We cannot load values larger than 0xFF (255) into
registers R0 to R12 using the MOV instruction. For
example, the following instruction is not valid:
• MOV R5,#0x999999 ;invalid instruction
• The reason is the fact that although the ARM instruction is
32-bit wide, only 8 bits of MOV instruction can be used as
an immediate value which can take values not larger than
0xFF (255).

Department of EECE-19ECS431-EMBEDDED SYSTEMS 22

Contd…
Classification of embedded system
ADD instruction:
• The ADD instruction has the following format:
• ADD Rd,Rn,Op2 ;ADD Rn to Op2 and store the result in Rd;Op2 can
be Immediate value #K (K is between 0 and 255) ;or Register Rm
• Example:
• MOV R1,#0x25 ;copy 0x25 into R1 (R1 = 0x25)
• MOV R7,#0x34 ;copy 0x34 into R1 (R7 = 0x34)
• ADD R5,R1,R7 ;add value R7 to R1 and put it in R5
• ;(R5 = R1 + R7)
• or
• MOV R1,#0x25 ;load (copy) 0x25 into R1 (R1 = 0x25)
• ADD R5,R1,#0x34 ;add 0x34 to R1 and put it in R5
• ;(R5 = R1 + 0x34)
Department of EECE-19ECS431-EMBEDDED SYSTEMS 23
ARM registers and ALU:
Classification of embedded system

Department of EECE-19ECS431-EMBEDDED SYSTEMS 24

ALU Instructions using GPRs:
Classification of embedded system

Department of EECE-19ECS431-EMBEDDED SYSTEMS 25

Contd…
Classification of embedded system

Department of EECE-19ECS431-EMBEDDED SYSTEMS 26

CPSR(Current Program Status Register)
Classification of embedded system
• Like all other microprocessors, the ARM has a flag
register to indicate arithmetic conditions such as the
carry bit. The flag register in the ARM is called the
current program status register (CPSR).

• In this section, we discuss various bits of this register

and provide some examples of how it is altered

Department of EECE-19ECS431-EMBEDDED SYSTEMS 27

CPSR(Current Program Status Register)
Classification of embedded system
• The status register is a 32-bit register. See Figure for the bits of the
status register. The bits C, Z, N, and V are called conditional flags,
meaning that they indicate some conditions that result after an
instruction is executed. Each of the conditional flags can be used to
perform a conditional branch (jump).

Department of EECE-19ECS431-EMBEDDED SYSTEMS 28

CPSR(Current Program Status Register)
Classification of embedded system
C, the carry flag
This flag is set whenever there is a carry out from the D31 bit. This
flag bit is affected after a 32-bit addition or subtraction. Chapter 4
shows how the carry flag is used.

Z, the zero flag

The zero flag reflects the result of an arithmetic or logic operation. If
the result is zero, then Z = 1. Therefore, Z = 0 if the result is not
zero. See Chapter 4 to see how we use the Z flag for looping.

Department of EECE-19ECS431-EMBEDDED SYSTEMS 29

CPSR(Current Program Status Register)
Classification
N: The negative flag
of embedded system
• Binary representation of signed numbers uses D31 as the sign
bit.
• The negative flag reflects the result of an arithmetic
operation.
• If the D31 bit of the result is zero, then N = 0 and the result is
positive.
• If the D31 bit is one, then N = 1 and the result is negative. The
negative and V flag bits are used for the signed number
arithmetic operations.
V: The overflow flag
• This flag is set whenever the result of a signed number
operation is too large, causing the high-order bit to overflow
into the sign bit.
• In general, the carry flag is used to detect errors in unsigned
Department of EECE-19ECS431-EMBEDDED SYSTEMS 30

arithmetic operations while the overflow flag is used to detect

CPSR(Current Program Status Register)
Classification
• The T flag bit is of embedded
used to indicatesystem
the ARM is in Thumb
state.
• The I and F flags are used to enable or disable the
interrupt.

S: Suffix and the status register

• Most of ARM instructions can affect the status bits of
CPSR according to the result.
• If we need an instruction to update the value of status
bits in CPSR, we have to put S suffix at the end of
instructions. That means, for example, ADDS instead of
ADD is used.
Department of EECE-19ECS431-EMBEDDED SYSTEMS 31
CPSR(Current Program Status Register)-Example:

Classification of embedded system

Department of EECE-19ECS431-EMBEDDED SYSTEMS 32

CPSR(Current Program Status Register)
Solution:

1) C = 1 because there is a carry beyond the D31 bit.

Classification
Z = 1 because the of
R2 embedded
(the result) hassystem
value 0 in it after the
addition.

2) C = 1 because there is a carry beyond the D31 bit.

Z = 0 because the R2 (the result) does not have value 0 in it
after the addition.
(R2=0x00000005)

Department of EECE-19ECS431-EMBEDDED SYSTEMS 33

CPSR(Current Program Status Register)
Example:

Classification of embedded system

Department of EECE-19ECS431-EMBEDDED SYSTEMS 34

CPSR(Current Program Status Register)

Department of EECE-19ECS431-EMBEDDED SYSTEMS 35

 PROCESSOR MODES
• The processor mode determines which registers are active and the
access rights to the cpsr register itself.
• Each processor mode is either privileged or nonprivileged

• Privileged mode allows full read-write access to the cpsr.

• Nonprivileged mode only allows read access to the control field in
the cpsr but still allows read-write access to the condition flags.

•There are seven processor modes in total: six privileged modes

abort, fast interrupt request, interrupt request, supervisor, system,
and undefined
nonprivileged mode :user

Department of EECE-19ECS431-EMBEDDED SYSTEMS 36

 PROCESSOR MODES

I=1, disables IRQ interrupts

F=1, disables FIQ interrupts
T=1 indicates Thumb state.
T=0 indicates ARM state.

Department of EECE-19ECS431-EMBEDDED SYSTEMS 37

PROCESSOR MODES
•The processor enters abort mode when there is a failed attempt to
access memory.
•Fast interrupt request and interrupt request modes correspond to
the two interrupt levels available on the ARM processor.
• Supervisor mode is the mode that the processor is in after reset
and is generally the mode that an operating system kernel operates
in.
•System mode is a special version of user mode that allows full
read-write access to the cpsr.
•Undefined mode is used when the processor encounters an
instruction that is undefined or not supported by the
implementation.
•User mode is used for programs and applications.

Department of EECE-19ECS431-EMBEDDED SYSTEMS 38

ARM Programmers model/BANKED
REGISTERS
Shows all 37 registers in the register file.
20 registers are hidden from a program at
different times. These registers are called
banked registers.

They are available only when the processor

is in a particular mode.

The processor mode can be changed by a

program that writes directly to the cpsr and
by hardware when the core responds to an
exception or interrupt

The following exceptions and interrupts

cause a mode change: reset, interrupt
request, fast interrupt request, software
interrupt, data abort, prefetch abort, and
undefined instruction.

Department of EECE-19ECS431-EMBEDDED SYSTEMS 39

BANKED REGISTERS
• The figure shows the core changing from user mode
to interrupt request mode,
• Which happens when an interrupt request occurs due
to an external device raising an interrupt to the
processor core.
• This change causes user registers r13 and r14 to be
banked. The user registers are replaced with registers
r13_irq and r14_irq, respectively.
• Note r14_irq contains the return address and r13_irq
contains the stack pointer for interrupt request mode.

• Another important feature to note is that the cpsr is

not copied into the spsr when a mode change is
forced due to a program writing directly to the cpsr.
• The saving of the cpsr only occurs when an
exception or interrupt is raised.

Department of EECE-19ECS431-EMBEDDED SYSTEMS 40

STATE AND INSTRUCTION SETS
STATE AND INSTRUCTION SETS
 STATE AND INSTRUCTION
SETS
• The state of the core determines which instruction set is being
executed.

• There are three instruction sets: ARM, Thumb, and Jazelle.

• Once in Thumb state the processor is executing purely Thumb 16-bit

instructions.

• When both J and T bits are 0, the processor is in ARM state and
executes ARM instructions-when power is applied to the processor.

• Jazelle executes 8-bit instructions and is a hybrid mix of software

and hardware designed to speed up the execution of Java
bytecodes. (24th Bit in CPSR)
Department of EECE-19ECS431-EMBEDDED SYSTEMS 43
 The ARM Memory Map
The ARM Memory Map
The Special Function Registers in ARM

• In ARM the R13, R14, R15, and CPSR (current program status
register) registers are called SFRs (special function registers) since
each one is dedicated to a specific function.

• GPRs (R0-R12) do not have any specific function and are used for
storing general data.

• Some ARM instruction formats (the Thumb) have only R0-7 but
every variation of ARM chip has R13-R15 SFRs.

• The Thumb instruction format is designed to compete with the 8-

and 16-bit microcontrollers and increase code density.
Department of EECE-19ECS431-EMBEDDED SYSTEMS 44
The ARM Memory Map
• Program Counter in the ARM
• The program counter is used by the CPU to point to the address of the
next instruction to be executed.

• As the CPU fetches the opcode from the program memory, the
program counter is incremented automatically to point to the next
instruction.

• The wider the program counter, the more memory locations a CPU
can access. That means that a 32-bit program counter can access a
maximum of 4G (232 = 4G) bytes of program memory locations.

• This means that the ARM family can access addresses 0x00000000 to
0xFFFFFFFF
Department of EECE-19ECS431-EMBEDDED SYSTEMS 45
The ARM Memory Map
• Although this 4G bytes of memory space can be allocated to on-
chip or off-chip memory; however, at the time of this writing, none
of the members of the ARM microcontroller family have the entire
4G bytes of on-chip memory populated

Department of EECE-19ECS431-EMBEDDED SYSTEMS 46

ARM Memory Map
The ARM Memory Map
• Memory space allocation in the ARM
• The 4G bytes of memory space can be divided into five sections
1. On-chip peripheral and I/O registers:
• Dedicated to general purpose I/O (GPIO) and special function
registers (SFRs) of peripherals such as timers, serial communication,
ADC, and so on.
• ARM uses memory-mapped I/O.
• The function and address location of each SFR is fixed by the chip
vendor at the time of design because it is used for port registers of
peripherals.
• The number of locations set aside for GPIO registers and SFRs
depends on the pin numbers and peripheral functions supported by
that chip.

Department of EECE-19ECS431-EMBEDDED SYSTEMS 48

The ARM Memory Map
2. On-chip data SRAM
• A RAM space ranging from a few kilobytes to several hundred kilobytes
is set aside mainly for data storage.

• The data RAM space is used for data variables and stack and is accessed
by the microcontroller instructions.

• The data RAM space is read/write memory used by the CPU for storage
of data variables, scratch pad, and stack

• A larger data SRAM size means more difficulties in managing these

RAM locations if you use Assembly language programming.

• Many of the ARM microcontrollers used in embedded products the

SRAM space is used for data- in some ARM both data and program
Department of EECE-19ECS431-EMBEDDED SYSTEMS 49

codes
The ARM Memory Map
3. On-chip EEPROM
• A block of memory from 1K bytes to several thousand bytes is set
aside for EEPROM memory
• Although in some applications the EEPROM is used for program code
storage, it is used most often for saving critical data.
• Not all ARM chips have on-chip EEPROM.

4. On-chip Flash ROM

• A block of memory from a few kilobytes to several hundred kilobytes
is set aside for program space.
• The program space is used for the program code.
• The Flash memory of code ROM is under the control of the PC
(program counter).
• The code ROM memory can also be used for storage of static fixed
data such as ASCII data strings and look-up tables.
Department of EECE-19ECS431-EMBEDDED SYSTEMS 50
The ARM Memory Map
5. Off-chip DRAM space
• A DRAM memory ranging from few megabytes to several hundred mega
bytes can be implemented for external memory connection.
• One can design an ARM-based system in which the RAM is used for both
data and program codes.
• we see in the x86 PCs. In such systems one connects the ARM CPU to
external DRAM and the DRAM memory is used for both code and data
• Memory mapped I/O in the ARM
• x86 had two distinct spaces: the I/O space and memory space
• I/O ports are accessed using IN and OUT instructions
• memory address space is accessed using the MOV instruction
• The ARM uses this 4 Giga bytes for both memory and I/O space.
• mapping of the I/O ports to memory space is called memory mapped I/O

Department of EECE-19ECS431-EMBEDDED SYSTEMS 51

The ARM Memory Map

An Example of ARM
Memory Allocation

Department of EECE-19ECS431-EMBEDDED SYSTEMS 52

The ARM Memory Map
• Example
A given ARM chip has the following address assignments. Calculate
the space and the amount of memory given to each section.
(a) Address range of 0x00100000 – 0x00100FFF for EEPROM
(b) Address range of 0x40000000 – 0x40007FFF for SRAM
(c) Address range of 0x00000000 – 0x0007FFFF for Flash
(d) Address range of 0xFFFC0000 – 0xFFFFFFFF for peripherals
Solution:
• (a) With address space of 0x00100000 to 00100FFF, we have 00100FFF – 00100000 =
0FFF bytes. Converting 0FFF to decimal, we get 4,095 + 1, which is equal to 4K bytes.

• (b) With address space of 0x40000000 to 0x40007FFF, we have 40007FFF – 40000000 =

7FFF bytes. Converting 7FFF to decimal, we get 32,767 + 1, which is equal to 32K bytes.

Department of EECE-19ECS431-EMBEDDED SYSTEMS 53

The ARM Memory Map
• Example 2
• Find the address space range of each of the following memory of an
ARM chip:
(a) 2 KB of EEPROM starting at address 0x80000000
(b) 16 KB of SRAM starting at address 0x90000000
(c) 64 KB of Flash ROM starting at address 0xF0000000
Solution:
(a) With 2K bytes of on-chip EEPROM memory, we have 2048 bytes
(2 × 1024 = 2048). This maps to address locations of 0x80000000 to
0x800007FF. Notice that 0 is always the first location.
(b) With 16K bytes of on-chip SRAM memory, we have 16,384 bytes
(16 × 1024 = 16,384), and 16,384 locations gives 0x90000000–
0x90003FFF.

Department of EECE-19ECS431-EMBEDDED SYSTEMS 54

LPC2148

• Development
Board
LPC2148

Pin Diagram
LPC2148
• Block Diagram
LPC2148
Applications
LPC2148
• Features
• PACKAGE: – 32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package with 64 Pins
• MEMORY: – 40 kB of on-chip static RAM – 512 kB of on-chip flash program memory
• ADC – Two 10-bit A/D converters(AD0 and AD1) provide a total of 14 analog inputs – conversion times as
low as 2.44 μs per channel
• DAC – Single 10-bit D/A converter provides variable analog output
• TIMERS – Two 32-bit timers/external event counters – Each timer with four capture and four compare
channels – Six PWM outputs – 1 Watchdog timer
• RTC – Low power real-time clock with independent power and dedicated 32 kHz clock input
• Serial Interfaces: – I2C-bus: • Two Fast I2C-bus with 400 kbit/s (I2C0,I2C1)
– UART communication: • Two UARTs (UART0,UART1)
– SPI (Serial Peripheral Interface) and SSP(Synchronous Serial Port)
• GPIO: – Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package
• INTERRUPTS: – Total of 22 interrupt Sources – Vectored interrupt controller with 16 configurable
priorities and vector addresses
• Speed : 60 MHz maximum CPU clock speed from programmable on-chip PLL with settling time of 100 μs
• OSCILLATOR: – On-chip integrated oscillator operates with an external crystal in range from 1 MHz to 30
MHz
• Power saving modes: – Idle mode , – Power-down mode
• CPU operating voltage : Range of 3.0 V to 3.6V (3.3 V ± 10 %) with 5 V tolerant I/O pads
• Other Features: • In-System / In-Application Programming (ISP/IAP) via on-chip boot-loader software.
• USB 2.0 Full Speed compliant Device Controller with 2 kB of endpoint RAM.
• In addition, the LPC2148 provide 8 kB of onchip RAM accessible to USB by DMA
LPC2148 – Bus Architecture
In LPC2148 three types of busses are used
to connect the core with other peripherals
on chip.

1. Local Bus to connect the onchip

memory controllers and fast GPIO’s
2. Advance High Performance Bus (AHB)
for interrupt controller
3. VLSI Peripheral Bus (VPB) for other
onchip peripherals.
• AHB acts as a bridge for VPB.
• VPB is mainly meant for connecting
slower peripherals with processor.
LPC2148 -Advanced
High performance Bus
(AHB)

• The ARM7 core is connected to the

Advanced High performance Bus (AHB)
• This is the Fastest Bus in ARM7 core
• Connected to the AHB is the vector
interrupt controller and a bridge to a
second bus called the VLSI peripheral bus
(VPB)
• Since the Interrupt vector controller is
responsible for managing all the device
interrupt sources, it is connected to the
ARM7 core by the fastest bus
LPC2148 -VLSI Peripheral Bus
[VPB]
• All the user peripherals are connected to the VPB
• The VBP bridge contains a clock divider, so the VPB bus can
be run at a slower speed than the ARM7 core and the AHB
Why VPB is operated at Slow Speeds
For two reasons
• First, we can run the user peripherals at a slower clock rate
than the main processor to conserve power.
• Second, it gives Philips the option of adding a slower
peripheral to the LPC2000 family without it becoming a
bottleneck on the AHB bus
What is the Optimum speed of VPB
• Currently all the on-chip peripherals are capable of running
at 60MHz so the VPB bus can be set to the same speed as
the AHB bus
• It is important to note that after reset the VPB divider is set
to divide down the AHB clock by four, so all the on-chip
peripherals will be running at ¼ the CPU clock frequency.
LPC2148 -Local Bus
• There is a third local bus which is used to
connect the on-chip Flash and RAM to the
CPU
• Connection of the program code and data
store to the ARM7 CPU via the AHB bus is
possible, but this introduces some
execution stalls because of contention on
the bus
• Using a separate local bus removes the
possibility of these stalls to give the best
processor performance.
Department of EECE-19ECS431-EMBEDDED SYSTEMS 64
Department of EECE-19ECS431-EMBEDDED SYSTEMS 65
Department of EECE-19ECS431-EMBEDDED SYSTEMS 66
Department of EECE-19ECS431-EMBEDDED SYSTEMS 67
Department of EECE-19ECS431-EMBEDDED SYSTEMS 68
Department of EECE-19ECS431-EMBEDDED SYSTEMS 69
Department of EECE-19ECS431-EMBEDDED SYSTEMS 70
Department of EECE-19ECS431-EMBEDDED SYSTEMS 71
Department of EECE-19ECS431-EMBEDDED SYSTEMS 72
Department of EECE-19ECS431-EMBEDDED SYSTEMS 73
Department of EECE-19ECS431-EMBEDDED SYSTEMS 74
Department of EECE-19ECS431-EMBEDDED SYSTEMS 75
Department of EECE-19ECS431-EMBEDDED SYSTEMS 76
ARM Family & Architecture

Department of EECE-19ECS431-EMBEDDED SYSTEMS 77