Computer Organization and Assembly Language

(CS2523)

Chapter 3 of
Computer Organization and Architecture, William Stallings, 11 th Edition,
Pearson

Instruction Execution Cycle: Chapter 2 of

Assembly Language for x86 Processors, Kip Irvine, 7th Edition, Pearson

Department of Computer Science,

Capital University of Science and Technology, Islamabad
Spring Semester, 2023
 Lecture Outlines
 Welcome to Assembly Language
 Applications of Assembly Language
 Assembly Language Comparison
 Programmer’s View of a Computer System/
Virtual Machine Concept

 General Concepts of a sequential

architecture/ Instruction Cycle
 Welcome to Assembly Language(AL)

• Oldest programming languages of all languages

• Provides direct access to computer hardware

• AL programmer knows a great deal about the

computer architecture and OS(operating
system)
 Welcome to Assembly Language(AL)

• Assembler
– A program that converts an AL source code
program to machine language
– Popular Assemblers
• MASM (Microsoft Assembler)
• EMU8086 (Microprocessor Emulator)
• TASM (Borland Turbo Assembler)
• NASM (The Netwide Assembler)
 Welcome to Assembly Language(AL)
• Software/Hardware Need
– Editor
• Text Editor for creating source files
– Assembler
– Linker
• Linker utility is required to produce executable file using libraries
– E-g; link32.exe
– Debugger
• For debugging/profiling of the program(errors detection/correction)
– CodeView for MASM
– Advanced Full Screen Debugger (AFD) for NASM
 Welcome to Assembly Language(AL)

• How does assembly language (AL) relate

to machine language?

• How do C++ and Java relate to AL?

• Is AL portable?
 Assembly Language Applications

– Business application for single platform

– Hardware device driver

– Business application for multiple

platforms

– Embedded systems & computer games

 Assembly vs High-Level Languages

Some representative types of applications:

Programmer’s View of a Computer System
A Concept by Tanenbaum
Virtual Machine Concept

Increased level Application Programs

of abstraction High-Level Language Level 5

Assembly Language Level 4

Operating System
Level 3

Instruction Set
Architecture Level 2

Microarchitecture Level 1
Each level
Digital Logic hides the
Level 0 details of the
level below it
 Programmer's View

Application Programs (Level 5)

Written in high-level programming languages
Such as Java, C++, Pascal, Visual Basic . . .
Programs compile into assembly language level (Level 4)

Assembly Language (Level 4)

Instruction mnemonics are used
Have one-to-one correspondence to machine language
Calls functions written at the operating system level (Level 3)
Programs are translated into machine language (Level 2)

Operating System (Level 3)

Provides services to level 4 and 5 programs
Translated to run at the machine instruction level (Level 2)
 Programmer's View

Instruction Set Architecture (Level 2)

Specifies how a processor functions
Machine instructions, registers, and memory are exposed
Machine language is executed by Level 1 (microarchitecture)
Microarchitecture (Level 1)
Controls the execution of machine instructions (Level 2)
Implemented by digital logic (Level 0)
Digital Logic (Level 0)
Implements the microarchitecture
Uses digital logic gates
Logic gates are implemented using transistors
 Assembly and Machine Language

Machine language
Native to a processor: executed directly by hardware
Instructions consist of binary code: 1s and 0s
Assembly language
Slightly higher-level language
Readability of instructions is better than machine language
One-to-one correspondence with machine language
instructions
Assemblers translate assembly to machine code
Compilers translate high-level programs to machine code
Either directly, or
Indirectly via an assembler
Compiler and Assembler
 Translating Languages

English: D is assigned the sum of A times B plus 10.

High-Level Language: D = A * B + 10

A statement in a high-level language is translated

typically into several machine-level instructions

Intel Assembly Language: Intel Machine Language:

mov eax, A A1 00404000
mul B F7 25 00404004
add eax, 10 83 C0 0A
mov D, eax A3 00404008
 Translating Languages

 These are called instructions, and they specify operations that

are to be performed by the processor.
 mov is a mnemonic for move,
 while mul is a mnemonic for multiply.
 Other common instructions include add, sub, and div.
 I trust you can figure out what operation these specify!
 Translating Languages

 Most instructions take two parameters.

 In the technical jargon, these are often known as operands.
 The first (on the left) is the destination,
 and the second (on the right) is the source.
 So, in the case of mov bx, 5
 this moves the literal value 5 into the destination register bx.
The order of these parameters matters, of course, because
you could not move the contents of the register bx into the
literal value 5!
 Translating Languages

 The mul instruction is a little bit strange because some of its

operands are implicit.
 That is, they are not explicitly specified as parameters.
 For the mul instruction,
the destination operand is hard-coded as the ax
register.
The source operand is the one that you pass as a
parameter: it can be either a register or a memory
location.
 Translating Languages

 Therefore, you could imagine that mul cx means

 mul ax, cx
 but you don't write it that way because the ax destination
register is implicit.
 Now, a mul instruction commands the processor to multiply the
destination operand by the source operand, and store the result
in the destination. In code, you can imagine that mul cx would
translate into ax = ax * cx.
 Translating Languages

 If you want to do 5 * 10, then:

mov ax, 5 ; ax = 5
mov cx, 10 ; cx = 10
mul cx ; ax = ax * cx
 Translating Languages-Registers
 Modern (i.e x86 and beyond) x86 processors have eight 32-bit general
purpose registers, as depicted in Figure:
 Translating Languages-Registers

 The register names are mostly historical.

 For example, EAX used to be called the accumulator since it
was used by a number of arithmetic operations, and
 ECX was known as the counter since it was used to hold a loop
index.
 Whereas most of the registers have lost their special purposes
in the modern instruction set, by convention, two are
reserved for special purposes — the stack pointer (ESP) and
the base pointer (EBP).
 Translating Languages-Registers

 For the EAX, EBX, ECX, and EDX registers, subsections may be
used. For example, the least significant 2 bytes of EAX can be
treated as a 16-bit register called AX. The least significant byte
of AX can be used as a single 8-bit register called AL, while the
most significant byte of AX can be used as a single 8-bit
register called AH. These names refer to the same physical
register.
 When a two-byte quantity is placed into DX, the update
affects the value of DH, DL, and EDX. These sub-registers are
mainly hold-overs from older, 16-bit versions of the
instruction set. However, they are sometimes convenient
when dealing with data that are smaller than 32-bits (e.g. 1-
byte ASCII characters).
 Translating Languages-Registers

 When referring to registers in assembly language, the names

are not case-sensitive. For example, the names EAX and eax
refer to the same register.
 General Concepts

• Basic Microcomputer Design

data bus

registers

I/O I/O
Central Processor Unit Memory Storage
Device Device
(CPU) Unit
#1 #2
ALU CU clock

control bus

address bus
 Basic Architecture

Processor
Control unit Datapath
ALU
Control
/Status
Controller
Registers
PC IR

I/O

Memory
 Datapath Operations
• Load
Processor
– Read memory location Control unit Datapath
into register ALU
• ALU operation Controller Control +1
/Status
– Input certain
registers through Registers
backstore
ALU, in register
• Store 10 11
– Write PC IR

register to memory
location
I/O
Memory
...
10
.1 .
1
.
 Control Unit
• Control unit: configures the datapath
operations Processor
– Sequence of desired operations Control unit Datapath
(“instructions”) stored in memory –
ALU
“program”
Controller Control
• Instruction cycle – broken into /Status
several sub-operations, each one
clock cycle, e.g.: Registers
– Fetch: Get next instruction into IR
– Decode: Determine what the
instruction means
– Fetch operands: Move data from PC IR R0 R1
memory to datapath register
– Execute: Move data through the
ALU I/O
– Store results: Write data from 100 load R0, Memory
...
500 10
register to memory M[500]
101 inc R1, R0
501
...
102 store M[501], R1
 Control Unit Sub-Operations

• Fetch Processor

– Get next Control unit Datapath

ALU
instruction into IR Controller Control
– PC: program /Status

counter, always Registers

points to next
instruction IR R0 R1
– IR: holds the
PC100 load R0, M[500]

fetched I/O
instruction 100 load R0, M[500] Memory
...
500 10
101 inc R1, R0
102 store M[501], R1
501
...
 Control Unit Sub-Operations

• Decode Processor
Control unit Datapath
– Determine what the
ALU
instruction means Controller Control
/Status

Registers

IR R0 R1
PC100 load R0, M[500]

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0
102 store M[501], R1
501
...
 Control Unit Sub-Operations

• Fetch operands Processor

Control unit Datapath
– Move data from
ALU
memory to datapath Controller Control
register /Status

Registers

10
PC100 0,IRM[500] R0 R1
load R

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0
102 store M[501], R1
501
...
 Control Unit Sub-Operations

• Execute Processor

– Move data Control unit Datapath

ALU
through the ALU Controller Control
– This particular /Status

instruction does Registers

nothing during
this sub-operation 10
PC100 0,IRM[500] R0 R1
load R

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0
102 store M[501], R1
501
...
 Control Unit Sub-Operations

• Store results Processor

– Write data from Control unit Datapath

ALU
register to Controller Control
memory /Status

– This particular Registers

instruction does
nothing during 10
R0 R1
this sub-operation PC100
load R
0,IRM[500]

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0
102 store M[501], R1
501
...
 Instruction Cycles

PC=100 Processor

FetchDecode Fetch Exec. Store Control unit Datapath

results ALU
ops
clk Controller Control
/Status

Registers

10
PC 100 IR R0 R1
load R0, M[500]

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0
102 store M[501], R1
501
...
 Instruction Cycles

PC=100 Processor

FetchDecode Fetch Exec. Store Control unit Datapath

results ALU
ops
clk Controller Control +1
/Status

PC=101
Store Registers
FetchDecode Fetch Exec.
results
ops
clk
10
PC 101 IR R0 11
inc R1, R0
R1

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0
102 store M[501], R1
501
...
PC=100 Processor

FetchDecode Fetch Exec. Store Control unit Datapath

results ALU
ops
clk Controller Control +1
/Status

PC=101
Store Registers
FetchDecode Fetch Exec.
results
ops
clk
IR 10
PC 101 inc R1, R0 R011
R1

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0
102 store M[501], R1
501
...
PC=100 Processor

FetchDecode Fetch Exec. Store Control unit Datapath

results ALU
ops
clk Controller Control +1
/Status

PC=101
Store Registers
FetchDecode Fetch Exec.
results
ops
clk
IR 10
PC 101 inc bx, ax 11
ax
bx

I/O

100 mov ax, M[500] Memory

...
500 10
101 inc bx, ax
102 store M[501], bx
501
...
 Instruction Cycles

PC=100 Processor

FetchDecode Fetch Exec. Store Control unit Datapath

results ALU
ops
clk Controller Control
/Status

PC=101
Store Registers
FetchDecode Fetch Exec.
results
ops
clk
10
PC 102 IR R0 11
store M[501], R1
R1
PC=102
FetchDecode Fetch Exec. Store
I/O
results ...
ops 100 load R0, M[500] Memory
clk 500 10
101 inc R1, R0
102 store M[501], R1 .
501 1 1

..
 Instruction Cycles

PC=100 Processor

FetchDecode Fetch Exec. Store Control unit Datapath

results ALU
ops
clk Controller Control
/Status

PC=101
Store Registers
FetchDecode Fetch Exec.
results
ops
clk
10
PC 102 IR 11
cx
store M[501], dx
dx
PC=102
FetchDecode Fetch Exec. Store
I/O
results ...
ops 100 load cx, M[500] Memory
clk 500 10
101 inc dx, cx
102 store M[501], dx .
501 1 1

..
 Architectural Considerations

• N-bit processor Processor

– N-bit ALU, registers, Control unit Datapath

ALU
buses, memory data Controller Control
interface /Status

– Embedded: 8-bit, Registers

16- bit, 32-bit

common PC IR
– Desktop/servers: 32-
bit, even 64 I/O

• PC size determines Memory

address space
 Architectural Considerations

• Clock frequency Processor

– Inverse of clock Control unit Datapath

ALU
period (f = Controller Control
1/T) /Status

– Must be longer Registers

than longest
register to register PC IR
delay in entire
processor
I/O
– Memory access is Memory
often the longest
Instruction Cycle
State Diagram
 Advantages of High-Level Languages

Program development is faster

High-level statements: fewer instructions to code
Program maintenance is easier
For the same above reasons
Programs are portable
Contain few machine-dependent details
Can be used with little or no modifications on
different machines
Compiler translates to the target machine language
However, Assembly language programs are not
portable
 Why Learn Assembly Language?

Two main reasons:

Accessibility to system hardware
Space and time efficiency
1. Accessibility to system hardware
Assembly Language is useful for implementing system
software
Also useful for small embedded system applications
2. Space and Time efficiency
Understanding sources of program inefficiency
Tuning program performance
Writing compact code
How a pipeline assembly code look like
How a pipeline assembly code look like