Boolean Theory

• Boolean theory provides the fundamentals for logic operators and operation to
perform Boolean algebra.
• Boolean algebra is a branch of mathematics that includes methods for manipulating
logical variables and logical expressions.
• The Greek philosopher Aristotle founded a system of logic based on only two types
of propositions: true and false.
• The English mathematician George Boole (1815–1864) sought to give symbolic form
to Aristotle’s system of logic—hence the name Boolean algebra.
• In the mid-twentieth century, Claude Shannon, an electrical engineer and
mathematician, applied Boole’s ideas to digital circuits.
Logic Variables and Logic Functions
• Like algebra, Boolean algebra is based on a set of rules that are derived from a small
number of basic assumptions. Logic values involve elements that take on one of two
values, 0 and 1. Therefore, a logic variable can only be equal to 0 or 1.
• A logic function is an expression, that describes the logic operations between its logic
variables. Similarly, a logic function can only be equal to 0 or 1.
BOOLEAN AXIOMS AND THEOREMS
• The basic logic operations include logic sum (+), logic product (·), and logic
complement (‘). i.e. OR, AND and NOT
• If a logic variable is true, its logic complement is false.
• In 1904 Huntington defined 6 postulates that must be satisfied, called Huntington’s
postulates
Postulates
• 1) Closure : Any logical operation yields a value in the set {0,1}.
• 2) Identity : (a) X + 0 = X (b) X·1=X
• 3) Commutative: (a) X+Y =Y+X (b) X·Y=Y·X
• 4) Distributive: (a) X·(Y+Z)=(X·Y)+(X·Z) (b) X+(Y·Z)=(X+Y) ·(X+Z)
• 5) Complements: (a) X+X’=1 (b) X·X’=0
• 6) Distinct: 0≠1
Theorems
• Theorem 1: (a) X+X=X (b) X.X=X
• Theorem 2: (a) X+1=1 (b)X·0=0
• Theorem 3: Involution : (X’)’=X
• Theorem 4: Associative : (a) X+(Y+Z)=(X+Y)+Z (b) X· (YZ)=(XY) ·Z
• Theorem 5: DeMorgan : (a) (X+Y)’=X’Y’ (b) (XY)’=X’+Y’
• Theorem 6: Absorption : (a) X+XY=X (b) X· (X+Y)=X

• All the theorems you can proof by truth table as well as with expression
Duality Principle
• The important property of Boolean algebra is called duality principle and it states
that every algebraic expression deducible from the postulates of Boolean algebra
remains valid if the operators and identity elements are interchanged.

• Interchange elements ={0,1}

• Interchange operator ={AND,OR}
Proof
• Theorem 1.(a) • Theorem 1.(b)
• X+X=X • X·X = X
• Proof: • Proof:
• X + X = (X + X).1 • X·X= XX + 0
• = (X + X)(X + X’) • = XX
• = X + XX’
• = XX + XX’
• =X+0
• = X(X + X’)
• =X
• = X·1
• =X
Theorems
• Theorem 2.(a) • Theorem 6.(a) • Theorem 6.(b)
• X+1=1 • X + XY = X • X(X+Y) = X
• Proof: • Proof: • Proof:
• X + 1= 1·(X+1) • X + XY = X·1 + XY • X(X+Y) = XX + XY
• = (X + X’)(X+1) • = X(1+Y) • =X+XY
• = X + X’ ·1 • = X ·1 • = X(1+Y)
• = X + X’ • =X • = X ·1
• =1 • =X
DeMorgan’s Theorem (a)

• Proof: (X+Y)’=X’Y’
• According to the complementing law, P+P’=1 and P·P’=0.

• So, if we take P=(X+Y), P’=(X+Y)’=X’Y’,

• So, (X+Y)+X’ ·Y’=((X+Y)+X’)((X+Y)+Y’)

• =(1+Y)(1+X)
• =(1).(1)
• =1
DeMorgan’s Theorem (b)
• Proof: (XY)’=X’+Y’
• According to the complementing law, P+P’=1 and P·P’=0.

• So, if we take P=(XY), P’=(XY)’=X’+Y’,

• So, XY+X’+Y’= (X’+Y’+X)(Y+X’+Y’)

• = (1+Y’)(1+X’)
• =1.1
• =1
Logic Gates
• Logic gates are electronic circuits that operate on one or more input signals to
produce an output signal .
• Electrical signals such as voltages or currents exist as analog signals having
values over a given continuous range, say, 0 to 3 V, but in a digital system
these voltages are interpreted to be either of two recognizable values, 0 or 1.
AND, OR, NOT Gates
Boolean Functions
• Boolean algebra is an algebra that deals with binary variables and logic operations. A
Boolean function described by an algebraic expression consists of binary variables.
• Exp: F1=X+Y’Z
• A Boolean function can be transformed from an algebraic expression into a circuit
diagram composed of logic gates connected in a particular structure.

• The operator precedence for evaluating Boolean expressions is (1) parentheses, (2)
NOT, (3) AND, (4) OR
Literals, Variables and Terms
• F2= X’Y’Z + X’YZ + XY’
• Variables = (X, Y, Z)
• Literals = (X’, Y’, Z, X’, Y, Z, X, Y’)
• Terms =(2 NOT term, 3 AND term and 1 OR term)
Minimization

• Minimization means reducing the number of literals. We can minimize the expression
with the help of postulates and theorems.

• F2 = X’Y’Z + X’YZ + XY’

• = X’Z(Y’+Y) + XY’
• = X’Z + XY’
Complement of a Function
• The complement of a function may be derived from DeMorgan's theorem

• DeMorgan’s theorems for any number of variables resemble the two variable case in
form and can be derived by successive substitutions similar to the method used in
the preceding derivation.

• (A+B+C+D+……..F)’ = A’B’C’D’…….F’
• (ABCD..F)’ = A’+ B’+ C’+ D’ + ……. + F’
Examples:
• Find the complement of the functions F1= X’YZ’ + X’Y’Z and F2= X(Y’Z’ +YZ) by
applying DeMorgan’s theorem:

• F1’ = (X’YZ’ + X’Y’Z’)’ = (X’YZ’)’(X’Y’Z)’

• = (X + Y’ + Z)(X + Y + Z’)

• F2’ = [X(Y’Z’ +YZ)]’ = X’ + (Y’Z’ + YZ)’ = X’ + (Y’Z’)’(YZ)’

• = X’ + (Y + Z)(Y’ + Z’)
• = X’ + YZ’ + Y’Z
Canonical and Standard Forms
• A binary variable may appear either in its normal form (x) or in its complement form
(x’). Now consider two binary variables x and y combined with an AND operation.
Since each variable may appear in either form, there are four possible combinations:
X’Y’, X’Y, XY’, XY.
• Each of this AND term is called a minterm or a standard sum.
• In similar fashion, all combination with a OR operator is called maxterms.
• Boolean functions expressed as a sum of minterms or product of maxterms are said
to be in canonical form.
• If you express the Boolean function in SOP and POS form then we call it standard
form.
• SOP form is used when output of logical expression is 1.
• POS form is used when output of a logical expression is 0.
Note*
• Generally, we use SOP form to calculate the sum of minterms and POS form to
calculate product of maxterms. If your initial expression is given in POS form and you
have to represent it in sum of minterms, you can convert your POS to SOP form to
proceed for the sum of minterms representation.

• Exp. You have given the following expression and asked to represent it in sum of
minterms form
• F = (A’+B)(A+B’) ------ POS Form
• = A’.A+A’.B’+AB+B.B’ -------(Multiply the product)
• = A’B’+AB --------(A.A’=0,B.B’=0) (SOP Form)
• To convert SOP to POS, we use distributive law
Three binary variable min terms and max
terms
Exp:
• Express the Boolean function F= A+ B’C as a sum of minterms.

• Sol: The function has three variables, A,B and C. The first term A is missing two
variables; therefore,
• A= A(B+B’) = AB + AB’
• The function is still missing C variable so,
• AB(C+C’)+ AB’(C+C’) = ABC + ABC’ + AB’C + AB’C’
• The second term B’C is missing A variable; hence,
• B’C = B’C(A+A’) = AB’C + A’B’C
• Combining all, F = ABC + ABC’ + AB’C + AB’C’ + A’B’C
• = A’B’C + AB’C’ + AB’C + ABC’ + ABC
• = m1+ m4 + m5 + m6 + m7 F(A,B,C) = (SOP)
Exp

• Express the Boolean function F= XY + X’Z as a product of maxterms.

• Sol: F= XY + X’Z = (XY + X’)(XY + Z)
• = (X + X’)(Y + X’)(X + Z)(Y + Z)
• = (X’ + Y)(X + Z)(Y + Z)
• The function has three variables: X, Y and Z.
• X’ + Y = X’ + Y + ZZ’ = (X’ + Y + Z)(X’ + Y + Z’)
• X + Z = X + Z + YY’ = (X + Y + Z)(X + Y’ + Z)
• Y + Z = Y + Z + XX’ = (X + Y + Z)(X’ + Y + Z)
• Now combining all term we will get, F = M0M2M4M5 = (0,2,4,5) (POS)
Consensus Theorem or Redundancy
Theorem Shortcut Method:
F1 = AB + A’C + BC 1) Three variable
= AB + A’C + BC(A+A’) 2) Each Variable comes twice
3) One variable is complemented
= AB + A’C + ABC + A’BC
= AB + A’C
If satisfy, remove the term without the
• F2 = (A + B)(A’ + C)(B + C) complemented variable
• = (A + B)(A’ + C)(B + C + 0)
For F1 that is BC and for F2 that is (B+C)
• = (A + B)(A’ + C)(B + C + AA’)
• = (A + B)(A + B + C)(A’ + C)(A’ + C + B)
• = (A + B)(A’ + C)
Some Problems and their Solutions
• P.1) Express the following function in sum of minterms and product of maxterms
• F = (xy+z)(y+xz)

Sum of minterms: F= (xy+z)(y+xz)

= xy + xyz + yz + xz (as, x.x=1)
= xyz + x’yz + xy’z +xyz’ (Adding the missing variable in each term)
=
Product of maxterms: F = (xy+z)(y+xz)
= (x+z)(y+z)(x+y)(y+z) (use distributive law)
= (x+y+z)(x’+y+z)(x+y’+z)(x+y+z’)
= (0,1,2,4)
Note: you can see from the both result that if you calculate sum of minterms for a particular
expression,
than you can easily find out the product of maxterms
by replacing the missing indices
Contd.
• P2) Minimize the following expression F= A’B(D’+C’D)+ B(A+A’CD)

• Sol: F = A’B(D’ + C’D) + B(A + A’CD)

• = B(A’D’ + A’C’D) + B(A + A’CD)
• = B(A’D’ + A’C’D + A + A’CD)
• = B(A’D’ + A + A’C’D + A’CD)
• = B(A’D’ + A + A’D) [as, C+C’=1]
• = B(A’D’ + A’D +A)
• = B(A’ + A)
• = B.1
• = B.
Contd.
• P3) Minimization F= xy + (xy)’wz
• Sol: Let A= xy and B= wz
• F = A + A’B
• F = (A+A’)(A+B)
• F = (A+B)
• =xy + wz
• P4) Simplified the expression for Y(A,B)=
• Sol: 0 index  00 in binary
• 2 index  10 in binary
• 3 index  11 in binary
• So the expression is Y = A’B’ + AB’ + AB = B’(A+A’) + AB = B’ + AB = (B’ + A)(B’ + B)
• = A + B’
Contd.
• P5) Simplify F = (A+B)(A+B’)(A’+B)(A’+B’)
• Sol: F = (A+B)(A+B’)(A’+B)(A’+B’)
• = (A + B.B’)(A’ + B.B’)
• = (A + 0)(A’ +0)
• = A.A’
• =0
OTHER LOGIC OPERATIONS
• Each of the 16 columns, F0 to F15, represents a truth table of one possible function
for the two variables, x and y. Note that the functions are determined from the 16
binary combinations that can be assigned to F.
• The 16 functions listed can be subdivided into three categories:
• 1. Two functions that produce a constant 0 or 1.
• 2. Four functions with unary operations: complement and transfer.
• 3. Ten functions with binary operators that define eight different operations: AND, OR,
NAND, NOR, exclusive‐OR, equivalence, inhibition, and implication.
• Although each function can be expressed in terms of the Boolean operators AND,
OR, and NOT .The Boolean expressions listed are simplified to their minimum
number of literals.
 Logic Families

 Introduction.
 Characteristics.
 Resistor Transistor Logic.
 Diode Transistor Logic.
 Transistor-Transistor Logic.
 Emitter coupled Logic.
AND logic:
OR logic:
 RTL is the first logic family which is
not available in monolithic form.

 The basic circuit of the RTL logic family is the NOR.

 Each input is associated with one resistor and

one transistor.
 The collector of the transistor are tied together at the output

 The voltage levels for the circuit are 0.2v for the low level and
from 1 to 3.6v for the high level
CIRCUIT DIAGRAM
A B Y=(A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
 Working:

 If any input is high. The corresponding transistor is driven

into saturation and the output goes low, regardless of the states
of the other transistor.

 If all inputs are low. Then all transistor are in cutoff state and
the output of the circuit goes high.
 DTL was first commercial available IC logic
family in 53/73 series.

 The basic circuit in the DTL logic is the NAND gate.

 Each input associated with one diode.

 The diode and resistor form an AND gate.

 The transistor services as a NOR gate

Circuit diagram
 Truth table

A B Y=A.B
0 0 1
0 1 1
1 0 1
1 1 0
 working :-
If any input is low:-
 The corresponding diodeconducts current through
Vccand resistor into the input node.

 The voltage at point p is equalto the input

voltage + diode drop.
 This is a insufficient voltage for conduction of a transistor.

 Since the voltage at point p is 0v then the transistor is cut off

state and the output is logic 1.
 If all inputs are high:-
 The transistor is driven into saturation region.

 The voltage at point p is high.

 Hence the output is low.

 It can perform many digital function and have achieved the
most popularity.

 TTL IC are given the numerical designation as 5400 and

7400 series

 The basic circuit of TTL with totem pole output stage is

NAND gate
 TTL uses a multi-miter transistor at the input and is fast
saturation logic circuit.
 The output transistor Q3 and Q4 form a totem- pole
connection.

 This extra output stage is known as totem-pole stage because

three output components Q3 and Q4 and Diode are stacked on
one another.
 This arrangement will increase the speed the speed of
operation and also increase output current capability.

 The function of diode in this circuit prevent both Q3 and Q4

being turned ON simultaneously.
Circuit Diagram
A B Y=A.B
0 0 1
0 1 1
1 0 1
1 1 0
 Working:-
• A=0, B=0; A=1, B=0; A=0, B=1;
 The emitter base junction of Q1 turns on.

 The collector potential of Q1 falls to 0v, then Q2 turns off.

 Therefore, at point M we have 0 volt i.e., the base voltage of
Q2 is 0volt.
 So that, Q2 is also turns off.

 But at the same time we have L=+VCC, this voltage is

applied on the base of Q4
 As a result transistor Q3 is turned ON.
 Therefore, the output voltage is given by
V0=+VCC-[Voltage drop in
R4+drop in diode ‘D’]
 A=1, B=1;
 When both input are high then emitter base junction of transistor
Q1 becomes reverse bias. Hence Q1 is turned off.

 However its collector base junction is forward bias, supplying base

current to the transistor Q2. Hence Q2 turns ON.

 As a result collector potential of Q2 becomes “0” volts.

 Now if L=0volt is applied to the base of Q3, it is turns off
.

 Atthe same time Q4 is turn ON. Then its collector

potential nearly equal to 0volts.

 Hence the output is low or logic o.

 ECL is non saturated digital logic family.

 The output of ECL provides OR and NOR function.

 Each input is connected to the base of transistor.

 The circuit consists of three parts.
1.differential input amplifier.
2.Internal temperature and voltage compensated bias network.
3.emittor follower output.

 The emitter output requires a pull down resistor for current

flow.

 In this logic family we consider the logic 0 as

-1.6v and logic 1 as -0.8v.
Circuit Diagram

V1 (NOR output)

V2 (OR output)

 When A=B=0 then Q1 transistors

OFF. So, Vc1 = 5v will reach at the
output V1. Then, the voltage at
Vc2 is 5v so Q2 ON. So, V2 is zero
since the output along short circuit
line is zero.

 Similarly remaining cases.

A B Y = A+B

0 0 1

0 1 0

1 0 0

1 1 0
 working:-
 A=0, B=0;

 So, the output of OR gate is logic ‘0’.

 Characteristics :-

 Propagation delay is very LOW(<1ns)

 ECL is fastest logic family.

 ECL circuit usually operate with –Ve supplies (+Ve

terminal is connected to ground).