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CISC and RISC

The document discusses CISC and RISC architectures. It describes the characteristics and examples of CISC and RISC processors. It also provides a comparative study of CISC and RISC architectures.

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G P ROHTIH
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19 views12 pages

CISC and RISC

The document discusses CISC and RISC architectures. It describes the characteristics and examples of CISC and RISC processors. It also provides a comparative study of CISC and RISC architectures.

Uploaded by

G P ROHTIH
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
Download as pptx, pdf, or txt
Download as pptx, pdf, or txt
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CISC AND RISC

INTRODUCTION

 IC-Instruction Count, CPI: Cycles per Instruction, CCT: Clock Cycle Time
 Cycle Clock Time – Hardware Technology
 CPI- Computer Organisation and ISA
 IC- Compiler Technology and ISA
INTRODUCTION(CONT..)

 Two Broad Classifications of ISA are:

 CISC(Complex instruction Set Computer(CISC)

 RISC(Reduced Instruction Set Computer(RISC)


CISC-TRADITIONAL TYPE

 The main idea behind CISC processors is that a single instruction can be used to do all
of the loading, evaluating and storing operations.
 The goal of the CISC approach is to minimize the number of instructions per
Programme.
 However, that increases the number of cycles per instruction.
 Large number of Addressing Modes
 Special Purpose Registers
 Variable Length Instructions
 Instruction Decoding / Control Unit design –more complex
 Pipeline implementation -Complex
CISC EXAMPLES
RISC

 Very widely used among many manufactures today


 It is also referred as Load and Store Architecture
 Only load and store instructions access memory and other
instructions operate on processor memory.
 Simple Architecture –Efficient Pipelining
 Simple instruction set –few addressing modes
 Large number of General Purpose registers
 Fixed length instructions-Easy and uniform instruction decoding
RISC EXAMPLE
CHARACTERISTIC OF CISC

 Complex instruction, hence complex instruction decoding.


 Instructions are larger than one-word size.
 Instruction may take more than a single clock cycle to get executed.
 Less number of general-purpose registers as operations get performed in memory
itself.
 Complex Addressing Modes.
 More Data types.
CHARACTERISTIC OF RISC

 Simpler instruction, hence simple instruction decoding.


 Instruction comes undersize of one word.
 Instruction takes a single clock cycle to get executed.
 More general-purpose registers.
 Simple Addressing Modes.
 Fewer Data types.
 A pipeline can be achieved.
RESULTS OF A COMPARATIVE STUDY
CHARACTERISTICS OF SOME CISCS, RISCS AND
SUPERSCALAR PROCESSORS
CISC VS RISC

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