Processor and computer

architecture
Learning objectives
• By the end of this chapter you should be able to:
• show understanding of the differences between RISC and CISC
processors
• show understanding of the importance/use of pipelining and
registers in RISC processors
• show understanding of interrupt handling on CISC and RISC
processors
• show awareness of the four basic computer architectures: SISD,
SIMD, MISD, MIMD
• show awareness of the characteristics of massively parallel
computers
The control unit
• The control unit ensure that each machine instruction is handled correctly when a
program is being executed.
• There are two ways that a control unit can be designed to allow it to perform its
function.
Method 1
• One method is for the control unit to be constructed as a logic circuit.
• This is called the hardwired solution .
• The machine-code instructions are handled directly by hardware.
Method 2
• The alternative is for the control unit to use microprogramming.
• In this approach, the control unit contains a ROM component in which is stored the
microinstructions or microcode for microprogramming.
• This is often referred to as firmware.
• The choice of which method is used is largely dependent on the type of processor
CISC
• Complex instruction set computing (CISC ) is a processor design,
where single instructions can execute several low-level operations
(such as a load from memory, an arithmetic operation, and a memory
store) or are capable of multi-step operations or addressing modes
within single instructions
• The design philosophy is to carry out a given task with as few lines of
assembly code as possible.
• Processor hardware must therefore be capable of handling more
complex assembly code instructions.
• CISC architecture is based on single complex instructions which need
to be converted by the processor into a number of sub-instructions to
carry out the required operation
CISC and RISC processors
RISC?
RISC, or Reduced Instruction Set Computer. is a type of microprocessor
architecture that utilizes a small, highly-optimized set of instructions,
rather than a more specialized set of instructions often found in other
types of architectures.
The RISC design philosophy is built on the use of less complex
instructions, which is done by breaking up the assembly
code instructions into a number of simpler single-cycle instructions.
RISC
• The following are characteristic of RISC processors:
• one cycle execution time: RISC processors have a CPI (clock per
instruction) of one cycle. This is due to the optimization of each
instruction on the CPU and a technique called pipelining
• pipelining: a technique that allows for simultaneous execution of
parts, or stages, of instructions to more efficiently process
instructions;
• large number of registers: the RISC design philosophy generally
incorporates a larger number of registers to prevent in large amounts
of interactions with memory
CISC and RISC processors
Multiplying Two Numbers in Memory
• Diagram representing the storage scheme for a generic
computer.
• The main memory is divided into locations numbered from
(row) 1: (column) 1 to (row) 6: (column) 4.
• The execution unit is responsible for carrying out all
computations.
• The execution unit can only operate on data that has been
loaded into one of the six registers (A, B, C, D, E, or F).
• Let's say we want to find the product of two numbers - one
stored in location 2:3 and another stored in location 5:2 - and
then store the product back in the location 2:3.
CISC and RISC processors
The CISC Approach
• The primary goal of CISC architecture is to complete a task in as
few lines of assembly as possible
• This is achieved by building processor hardware that is capable
of understanding and executing a series of operations.
• A CISC processor would come prepared with a specific
instruction (we'll call it "MULT").
• When executed, this instruction loads the two values into
separate registers, multiplies the operands in the execution
unit, and then stores the product in the appropriate register.
• Thus, the entire task of multiplying two numbers can be
completed with one instruction:
MULT 2:3, 5:2
CISC and RISC processors
The CISC Approach

• MULT is what is known as a "complex instruction."

• It operates directly on the computer's memory banks and does not
require the programmer to explicitly call any loading or storing
functions.
• It closely resembles a command in a higher level language.
• For instance, if we let "a" represent the value of 2:3 and "b"
represent the value of 5:2, then this command is identical to the C
statement "a = a * b."
CISC and RISC processors
The CISC Approach

Advantage:-
• Compiler has to do very little work to translate a high-level language
statement into assembly
• Length of the code is relatively short
• Very little RAM is required to store instructions
• The emphasis is put on building complex instructions directly into the
hardware.
The RISC Approach
• RISC processors only use simple instructions that can be
executed within one clock cycle.
• Thus, the "MULT" command described above could be
divided into three separate commands:
1. "LOAD," which moves data from the memory bank to a
register,
2. "PROD," which finds the product of two operands
located within the registers, and
3. "STORE," which moves data from a register to the
memory banks.
• programmer would need to code four lines of assembly:
LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A
The RISC Approach

• At first, this may seem like a much less efficient way of completing the
operation.
• Because there are more lines of code, more RAM is needed to store
the assembly level instructions.
• The compiler must also perform more work to convert a high-level
language statement into code of this form.
The RISC Approach
1. Each instruction requires only one clock cycle to execute, the entire
program will execute in approximately the same amount of time as
the multi-cycle “MULT” command.
2. These RISC “reduced instructions” require less transistors of
hardware space than the complex instructions, leaving more room
for general purpose registers. Because all of the instructions
execute in a uniform amount of time (i.e. one clock)
3. Pipelining is possible.
Comparison of RISC with CISC
 Pipelining
• The forces for RISC processors was it enable efficient pipelining.
• Pipelining is a form of parallelism applied specifically to instruction execution.
• Pipelining allows several instructions to be processed simultaneously without
having to wait for previous instructions to be completed.
• The underlying principle of pipelining is that the fetch -decode-execute cycle

• That can be separated into a number of stages

• One possibility is a five-stage model consisting of:
• instruction fetch (IF) Clock cycles
• instruction decode (ID)
• operand fetch (OF)
• instruction execute (IE)
• result write back (WB).
Pipelining
• To demonstrate how pipelining works, we will consider a program which has
six instructions (A, B, C, D, E and F).
• This functionality clearly requires processors with several registers to store
each of the stages
Handling of interrupt in pipelining
• One issue that has to be dealt with regarding a pipelined processor is
interrupt handling.
• In the pipelined system there will be five instructions in the pipeline when an
interrupt occurs.
• One option for handling the interrupt is to erase the pipeline contents for the
latest four instructions to have entered.
• Then the normal interrupt-handling routine can be applied to the remaining
instruction.
• The other option is to construct the individual units in the processor with
individual program counter registers.
• This allows current data to be stored for all of the instructions in the pipeline
while the interrupt is handled.
Parallel processing

Parallel processor systems

➔There are many ways that parallel
processing can be carried out.
➔The four categories of basic computer
architecture presently used are described
below.
Single instruction Stream Single Data stream
➔ uses a single processor that can handle a single instruction and
which also uses one data source at a time.
➔ Each task is processed in a sequential order.
➔ Since there is a single processor, this architecture does not allow for
parallel processing.
single instruction multiple data

SIMD (single instruction multiple data) uses many processors.

Each processor executes the same instruction but uses different data
inputs – they are all doing the same calculations but on different data
at the same time.
single instruction multiple data

➔ SIMD are often referred to as array processors; they have a

particular application in graphics cards.
➔ For example, suppose the brightness of an image made up of 4000
pixels needs to be increased.
➔ Since SIMD can work on many data items at the same time, 4000
small processors (one per pixel) can each alter the brightness of
each pixel by the same amount at the same time.
➔ This means the whole of the image will have its brightness increased
consistently
MISD (multiple instruction single data)
➔ MISD (multiple instruction single data) uses several
processors.
➔ Each processor uses different instructions but uses the same
shared data source.
 MIMD (multiple instruction multiple data)

➔ MIMD (multiple instruction multiple data) uses multiple processors.

➔ Each one can take its instructions independently, and each processor
can use data from a separate data source (the data source may be a
single memory unit which has been suitably partitioned).
➔ The MIMD architecture is used in multicore systems (for example, by
super computers or in the architecture of multi-core chips).
MIMD (multiple instruction multiple data)-Factors
➔ When carrying out parallel processing, processors need to
be able to communicate.
➔ The data which has been processed needs to be transferred
from one processor to another.
➔ When software is being designed, or programming
languages are being chosen, they must be capable of
processing data from multiple processors at the same time.
➔ It is a much faster method for handling large volumes of
independent data; any data which relies on the result of a
previous operation (dependent data) would not be suitable
in parallel processing.
Parallel computer systems
• SIMD and MIMD are the most commonly used
processors in parallel processing.
• A number of computers (containing SIMD
processors) can be networked together to form a
cluster.
• The processor from each computer forms part of a
larger pseudo-parallel system which can act like a
super computer also refered to this as grid
computing
 Massively parallel computers
➔ Massively parallel computer is
made by linking together of a
➔ number of computers,
effectively forming one
machine with several thousand
processors.
➔ Needed to solve increasingly
complex problems in the world
of science and mathematics.
➔ In massively parallel computers,
each processor will carry out
part of the processing and
communication between
computers is achieved via
interconnected data pathways