Digital Basics Training

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Contents
• Digital Logic Design Overview
• Introduction
• Digital Logic System Basic
• Basic Digital Logic Combinational Gates
• Basic Digital Sequential/Memory 1 bit memory
• Demorgan's/Karnaugh Law
• PoS & SoP
• RAM/ROM introduction
• Conclusion
Overview of Digital Logic Design
• Digital Logic Design is the process of creating digital circuits that
perform specific functions
• It involves the use of logic gates. Flip-flops, multiplexers & other
digital components to create a circuit that performs a specific
task/function
• Digital logic design is based on Boolean Algebra, mathematical system
for representing & manipulating logical expressions.
• Digital Logic Designs are used in applications like computer systems,
mobile, communication, remote sensing, bio-medical, etc applications
Introduction to Digital Logic Basics
• Hardware/functional system consists of few system building blocks
• These are called logic gates
• AND, OR, NOT, …
• NAND, NOR, XOR..

• Logic Gates are built using Transistors

• NOT/Inverter Gate can be implemented with 2 transistors in CMOS Logic
• NAND Gare requires 4 transistors

• Transistors are the fundamental devices

• IC 7400 with TTL comprising NAND gate with 4 transistors
• Pentium processor consists of millions of transistors
• Now we can build chips with more than billion transistors
Basic digital building blocks
and design concepts
This chapter is mostly a recap of your academic course work in digital electronics. It is
best to refresh and understand the design blocks from a large scale integration
perspective. The individual functional knowledge of each of these tiny elements are
not sufficient by themselves. When each block is looked at from a design integration
perspective, the inherent limitations of these elements and new possibilities simply
become clear to the designer.
Basic Logic Gates
• AND gate ( Multiplication )
• OR gate ( Addition )
• Not gate ( Inverter )
• Buffer
• NAND gate
• NOR gate
• XOR gate ( Exclusive OR )
• XNOR gate ( Exclusive OR )
 De-Morgan's Theorem

• The rules of De-Morgan's theorem are produced from the Boolean expressions for OR, AND, and
NOT using two input variables x and y. The first theorem of De Morgan's says that if we perform
the AND operation of two input variables and then perform the NOT operation of the result, the
result will be the same as the OR operation of the complement of that variable. The second
theorem of De Morgan says that if we perform the OR operation of two input variables and then
perform the NOT operation of the result, the result will be the same as the AND operation of the
complement of that variable.
Input variables Output Condition
A B AND NAND OR NOR
0 0 0 1 0 1
0 1 0 1 1 0
1 0 0 1 1 0
1 1 1 0 1 0
• According to the first theorem, the complement result of the AND
De-Morgan's First Theorem

operation is equal to the OR operation of the complement of that

variable. Thus, it is equivalent to the NAND function and is a negative-
OR function proving that (A.B)' = A'+B'

Inputs Output For Each Term

A B A.B (A.B)' A' B' A'A+B'

0 0 0 1 1 1 1

0 1 0 1 1 0 1

1 0 0 1 0 1 1

1 1 1 0 0 0 0
De-Morgan's Second Theorem
• According to the second theorem, the complement result of the OR
operation is equal to the AND operation of the complement of that
variable. Thus, it is the equivalent of the NOR function and is a
negative-AND function proving that (A+B)' = A'.B'
Inputs Output For Each Term
A B A+B (A+B)' A' B' A'.B'
0 0 0 1 1 1 1
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 0
 De-Morgan's Theorem Problems
• Let's take some examples in which we take some expressions and apply De Morgan's theorems.
Example : ((A+BC')'+D(E+F')')'
• For applying the De Morgan's theorem on this expression, we have to follow the following expressions:
• 1) In complete expression, first, we find those terms on which we can apply the De Morgan's theorem and treat each term as a single variable

So,

2) Next, we apply DeMorgan's first theorem. So,

3) Next, we use rule number 9, i.e., (A=(A')') for canceling the double bars.

4) Next, we apply DeMorgan's second theorem. So,

5) Again apply rule number 9 to cancel the double bar

Karnaugh Maps

• Another approach to simplification is called

the Karnaugh map, or K-map.
• A K-map is a truth table graph, which aids in
visually simplifying logic. • It is useful for up
to 5 or 6 variables, and is a good tool to help
understand the process of logic simplification.
• The algebraic approach we have used
previously is also used to analyse complex
circuits in industry (computer analysis).
• At the right is a 2-variable K-map.
• This very simple K-map demonstrates that
an n-variable K-map contains all the
combination of the n variables in the K- map Two-Variable K-map, labelled for SOP terms. Note the four
space squares represent all the combinations of the two K-map
variables, or minterms, in x & y (example above).
Three-Variable Karnaugh Map
• A useful K-map is one of three variables.
• Each square represents a 3-variable minterm
or maxterm.
• All of the 8 possible 3-variable terms are
represented on the K-map.
• When moving horizontally or vertically, only 1
variable changes between adjacent squares,
never 2. This property of the Kmap, is unique
and accounts for its unusual numbering
system.
• The K-map shown is one labelled for SOP
terms. It could also be used for a POS problem,
but we would have to re-label the variables.
Four Variable Karnaugh Map
• A 4-variable K-map can simplify problems of four
Boolean variables.*
• The K-map has one square for each possible minterm
(16 in this case).
• Migrating one square horizontally or vertically never
results in more than one variable changing (square
designations also shown in hex).

• * Note that on all K-maps, the left and right edges

are a common edge, while the top and bottom edges
are also the same edge. Thus, the top and bottom
rows are adjacent, as are the left and right columns.
Rules to obtain the most simplified expression
•Simplification of logic expression using Boolean algebra is awkward because:
• it lacks specific rules to predict the most suitable next step in the simplification process
• it is difficult to determine whether the simplest form has been achieved.
•A Karnaugh map is a graphical method used to obtained the most simplified
form of an expression in a standard form (Sum-of-Products or Product-of-
Sums).
•The simplest form of an expression is the one that has the minimum number of
terms with the least number of literals (variables) in each term.
•By simplifying an expression to the one that uses the minimum number of
terms, we ensure that the function will be implemented with the minimum
number of gates.
•By simplifying an expression to the one that uses the least number of literals for
each terms, we ensure that the function will be implemented with gates that
have the minimum number of inputs
Three-Variable K-Maps

f   (0,4)  B C f   (4,5)  A B f   (0,1,4,5)  B f   (0,1,2,3)  A

BC BC BC BC
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1

1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0

f   (0,4)  A C f   (4,6)  A C f   (0,2)  A C f   (0,2,4,6)  C

BC BC BC BC
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
0 0 1 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1
1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1
Four-Variable K-Maps

CD CD CD CD
00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10
AB AB AB AB
00 1 0 0 0 00 0 0 0 0 00 0 0 0 0 00 0 0 0 0

01 0 0 0 0 01 0 1 0 0 01 0 0 0 0 01 1 0 0 1

11 0 0 0 0 11 0 1 0 0 11 0 1 1 0 11 0 0 0 0

10 1 0 0 0 10 0 0 0 0 10 0 0 0 0 10 0 0 0 0

f   (0,8)  B  C  D f   (5,13)  B  C  D f   (13,15)  A  B  D f   (4,6)  A  B  D

CD CD CD CD
00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10
AB AB AB AB
00 0 0 1 1 00 0 0 0 0 00 0 0 1 1 00 1 0 0 1

01 0 0 1 1 01 1 0 0 1 01 0 0 0 0 01 0 0 0 0

11 0 0 0 0 11 1 0 0 1 11 0 0 0 0 11 0 0 0 0

10 0 0 0 0 10 0 0 0 0 10 0 0 1 1 10 1 0 0 1

f   (2,3,6,7)  A  C f   (4,6,12,14)  B  D f   (2,3,10,11 )  B  C f   (0,2,8,10)  B  D

Four-Variable K-Maps
CD CD CD CD
00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10
AB AB AB AB
00 0 0 0 0 00 0 0 1 0 00 1 0 1 0 00 0 1 0 1

01 1 1 1 1 01 0 0 1 0 01 0 1 0 1 01 1 0 1 0

11 0 0 0 0 11 0 0 1 0 11 1 0 1 0 11 0 1 0 1

10 0 0 0 0 10 0 0 1 0 10 0 1 0 1 10 1 0 1 0

f   (0, 3,5, 6, 9,10,12,15) f   (1, 2, 4, 7,8,11,13,14)

f   (4, 5, 6, 7)  A  B f   (3, 7,11,15)  C  D
f  A  BC D f  A  B C D

CD CD CD CD
00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10
AB AB AB AB
00 0 1 1 0 00 1 0 0 1 00 0 0 0 0 00 1 1 1 1

01 0 1 1 0 01 1 0 0 1 01 1 1 1 1 01 0 0 0 0

11 0 1 1 0 11 1 0 0 1 11 1 1 1 1 11 0 0 0 0

10 0 1 1 0 10 1 0 0 1 10 0 0 0 0 10 1 1 1 1

f   (1, 3,5, 7, 9,11,13,15) f   (0,2,4,6,8,10,12,14) f   (4,5,6,7,12,13,14,15) f   (0,1,2,3,8,9,10,11)

f D f D f B f  B
 Design of combinational digital circuits
• Steps to design a combinational digital circuit:
• From the problem statement derive the truth table
• From the truth table derive the unsimplified logic expression
• Simplify the logic expression
• From the simplified expression draw the logic circuit
• Example: Design a 3-input (A,B,C) digital circuit that will give at its output (X) a logic 1 only if the binary
number formed at the input has more ones than zeroes

Inputs Output
A B C X X   (3, 5, 6, 7)
0 0 0 0 0
1 0 0 1 0 X
BC
2 0 1 0 0 A 00 01 11 10
3 0 1 1 1 0 0 0 1 0
4 1 0 0 0 1 0 1 1 1
5 1 0 1 1
6 1 1 0 1
7 1 1 1 1 X  AC  AB  BC
A B C
 Design of combinational digital circuits (Cont.)
• Example: Design a 4-input (A,B,C,D) digital circuit that will give at its output (X) a logic 1 only if
the binary number formed at the input is between 2 and 9 (including).
Inputs Output
A B C D X X   (2,3,4,5,6,7,8,9)
0 0 0 0 0 0
1 0 0 0 1 0 X
2 0 0 1 0 1 CD
3 0 0 1 1 1 AB 00 01 11 10
4 0 1 0 0 1 00 0 0 1 1 Same
5 0 1 0 1 1
01 1 1 1 1
6 0 1 1 0 1
7 0 1 1 1 1 11 0 0 0 0
8 1 0 0 0 1 10 1 1 0 0
9 1 0 0 1 1
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 0 X  AC  AB  A B C
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 0 A B C D X
 Generalized FSM model: Moore and Mealy

Moore machine Mealy machine

• Outputs are a function of current state
• Outputs change synchronously with state • Outputs depend on state and on inputs
changes • Input changes can cause
immediate output changes (asynchronous)
inputs
combinational
logic for
logic for inputs outputs
logic for outputs
next state
reg outputs outputs
combinational
logic for reg
next state
state feedback
state feedback
 Mealy machine for a 1010 detector

• A sequence detector is a sequential state •State assignments: Let S0 = 00

machine. In a Mealy machine, output depends S1 = 01
on the present state and the external input (x). S2 = 10
Hence in the diagram, the output is written
outside the states, along with inputs. The state S3 = 11
diagram of a Mealy machine for a 1010 The above state table becomes
detector is:
Excitation table
• Four states will require two flip flops. • K-maps to determine inputs to D Flip flop:
Consider two D flip flops. Their excitation
table is shown below.
• Excitation table:
Circuit diagram for the sequence detector
 Random Access Memory (RAM) and Read Only Memory (ROM)
• Random Access Memory (RAM) is a type of computer memory that is used to
temporarily store data that the computer is currently using or processing. RAM is
volatile memory, which means that the data stored in it is lost when the power is
turned off. RAM is typically used to store the operating system, application programs,
and data that the computer is currently using.
• Read Only Memory (ROM) is a type of computer memory that is used to
permanently store data that does not need to be modified. ROM is non-volatile
memory, which means that the data stored in it is retained even when the power is
turned off. ROM is typically used to store the computer’s BIOS (basic input/output
system), which contains the instructions for booting the computer, as well as firmware
for other hardware devices.

• Types of Memory
• Primary memory (RAM and ROM)
• Secondary memory (Hard Drive, CD, etc).
Random Access Memory (RAM)
• It is also called read-write memory or the main • Types of Random Access Memory (RAM)
memory or the primary memory. • 1. Static RAM: SRAM stands for Static Random
• The programs and data that the CPU requires Access Memory. It is a type of semiconductor which is
during the execution of a program are stored in this widely used in computing devices and
memory. microprocessors.

• It is a volatile memory as the data is lost when the • 2. Dynamic RAM: DRAM stands for Dynamic
power is turned off Random Access Memory. It is made of Capacitors and
has smaller data life span than Static RAM
 Read-Only Memory (ROM)

• Stores crucial information essential to operate Types of Read-Only Memory (ROM)

the system, like the program essential to boot 1. PROM (Programmable read-only memory): It can be
the computer. programmed by the user. Once programmed, the data and
instructions in it cannot be changed.
• It is non-volatile. 2. EPROM (Erasable Programmable read-only memory): It can
• Always retains its data. be reprogrammed. To erase data from it, expose it to ultraviolet
• Used in embedded systems or where the light. To reprogram it, erase all the previous data.
programming needs no change. 3. EEPROM (Electrically erasable programmable read-only
memory): The data can be erased by applying an electric field,
• Used in calculators and peripheral devices. with no need for ultraviolet light. We can erase only portions of the
• ROM is further classified into four types- chip.
MROM, PROM, EPROM, and EEPROM. 4. MROM(Mask ROM): Mask ROM is a kind of read-only
memory, that is masked off at the time of production. Like other
types of ROM, mask ROM cannot enable the user to change the
data stored in it. If it can, the process would be difficult or slow.
Difference between RAM and ROM
 RAM address decoder
• The address decoder required for the simple 4x4 bit
random access memory circuit. While nChipSelect is high, all
word-lines are disabled. When nChipSelect is low, the decoder
decodes the 2-bit input on the A1,A0 input lines and enables the
corresponding word-line.
• When the number of memory addresses becomes very large, the
addresses are usually split into multiple parts, each of which is
decoded separately. For example, a 64 Mbit RAM organized as
2 M words of 32 bits might include 1024 blocks of 512 word
lines of 128 bits. Then, a first 10-to-1024 decoder would enable
one of the 1024 blocks, while a second 9-to-512 decoder enables
one of the 512 word lines of the selected block, and a third stage
of 2-to-4 decoders selects one 32-bit group out of the 128-bits of
the block. This organization avoids very long bit lines, which are
limited to at most a thousand connections due to electrical
effects. Naturally, each block requires its own second-level (here
9-to-512) and third-level (here 2-to-4) decoders, unless it is
possible to share the second-level decoders between a few
blocks.
 Read-Only Memory (ROM) Decoding

When both the inputs are 0, then only D is 1

and rest are 0, when input is 01, then, only D
is high and so on. (Just remember that if the
input combination of the decoder resolves to a
particular decimal number d, then at the
output side the terminal which is at position d
+ 1 from the top will be 1 and rest will be 0).
Now, since we want each address to store 4 –
bits in the 4 x 4 ROM, so, there will be 4 OR
gates, with each of the 4 outputs of the
decoder being input to each one of the 4 OR
gates, whose output will be the output of the
ROM
Design the following gates using of 2:1 Muxes

Construct a 16:1 Mux with two 8:1 mux and one 2:1 Mux
NOT, AND, OR, XOR gates
Design the following gates using of 2:1 Muxes

Show the AOI implementation of a 2:1 Mux Convert AOI implementation of a 2:1 Mux to 2
input NAND implementation
So, the waveform for NOT gate is not:
CMOS Inverter

(a) Circuit schematic for a CMOS inverter

(b) Simplified operation model with a high input applied
(c) Simplified operation model with a low input applied

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CMOS Inverter Operation
• When VI is pulled high (VDD), the PMOS inverter is turned off, while the
NMOS is turned on pulling the output down to VSS

• When VI is pulled low (VSS), the NMOS inverter is turned off, while the
PMOS is turned on pulling the output up to VDD

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CMOS Inverter Layout
• Two methods of laying
out a CMOS inverter
are shown
• The PMOS transistors
lie within the n-well,
whereas the NMOS
transistors lie in the p-
substrate
• Polysilicon is used to
form common gate
connections, and metal
is used to tie the two
drains together

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Static Characteristics of the CMOS Inverter
• The figure shows the
two modes of static
operation with the
circuit and simplified
models
• Notice that VH = 5V and
VL = 0V, and that ID = 0A
which means that there
is no static power
dissipation
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CMOS Voltage Transfer Characteristics
• The VTC shown is for a CMOS
inverter that is symmetrical (KP
= KN)
• Region 1: vO = VH
vI < VTN
• Region 2: |vDS| ≥ |vGS – VTP|
• Region 4: vDS ≥ vGS – VTN
• Region 5: vO = VL
vI > VDD – |VTP|

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CMOS Voltage Transfer Characteristics
• The simulation
result shows the
varying VTC of the
inverter as VDD is
changed
• The minimum
voltage supply for
a certain MOS
technology is
2VT∙ln(2)

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CMOS Voltage Transfer Characteristics
• The simulation result
shows the varying
VTC of the inverter
as KN/KP = KR is
changed
• For KR > 1 the NMOS
current drive is
greater and it forces
vI < VDD/2
• For KR < 1 the PMOS
current drive is
greater and it forces
vI > VDD/2

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Noise Margins for the CMOS Inverter
• Noise margins
are defined by
the regions
shown in the
given figure

NML = VIL – VOL

NMH = VOH – VIH

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Noise Margins for the CMOS Inverter
4. 0

3. 5

3. 0
NM
H

Noi se Margi n ( Vol t s)

2. 5

2. 0

1. 5

NM
1. 0 L

0. 5
0 1 2 3 4 5 6 7 8 9 10 11
K
R

F igu re 8.8 - Nois e m a rgin s vers u s K R for t h e CMO S in vert er wit h

VDD = 5 V a n d VTN = -VTP = 1 V.

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Propagation Delay Estimate

• The two modes of capacitive charging that contribute to

propagation delay

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Propagation Delay Estimate
   VH  VTN   2VTN 
 PHL  RonN C ln 4   1  
   VH  VL   VH  VTN 
1
RonN 
K n VH  VTN 
 PHL   PLH
p    PHL
2
• If it is assumed the inverter in “symmetrical”,
(W/L)P = 2.5(W/L)N, then τPLH = τPHL
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Rise and Fall Times
• The rise and fall times are given by the following
expressions:

t f  2 PHL
t r  2 PLH

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Shorthand Notation for NMOS and PMOS
Transistors

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A digital signal is never so!
https://www.onsemi.com/pub/Collateral/AND9075-D.PDF
Schematic, Stick Diagram and Layout of Logic Gates
Sequential Logic Latches & Flip-flops

Introduction
• Memory Elements
• Pulse-Triggered Latch
S-R Latch
Gated S-R Latch
Gated D Latch
• Edge-Triggered Flip-flops
S-R Flip-flop
D Flip-flop
J-K Flip-flop
T Flip-flop
• Asynchronous Inputs
Introduction

 A sequential circuit consists of a feedback path, and employs some memory

elements.
 There are two types of sequential circuits:
synchronous: outputs change only at specific time
asynchronous: outputs change at any time
 Multivibrator: a class of sequential circuits. They can be:
Bistable (2 stable states)
Monostable or one-shot (1 stable state)
Astable (no stable state)
 Bistable logic devices: latches and flip-flops.
Memory element
• Memory element: a device which can remember value indefinitely, or
change value on command from its inputs.

Memory Q
command element stored value

• Characteristic table:
Command Q(t) Q(t+1)
(at time t) Q(t): current state
Set X 1 Q(t+1) or Q+: next state
Reset X 0
Memorise / 0 0
No Change 1 1
Memory Elements
• Memory element with clock. Flip-flops are memory elements that
change state on clock signals.

Memory Q
command element stored value

clock
• Clock is usually a square wave
Positive pulses

Positive edges Negative edges

Memory Elements
 Two types of triggering/activation:
pulse-triggered
edge-triggered
 Pulse-triggered
latches
ON = 1, OFF = 0
 Edge-triggered
flip-flops
positive edge-triggered (ON = from 0 to 1; OFF = other time)
negative edge-triggered (ON = from 1 to 0; OFF = other time)
 S R Q Q'
0 0 NC NC No change. Latch
S Q
S-R Latch
remained in present state.
1 0 1 0 Latch SET.
R Q' 0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.

 Complementary outputs: Q and Q'. R

Q
 When Q is HIGH, the latch is in SET state.
 When Q is LOW, the latch is in RESET state. S
Q'

 For active-HIGH input S-R latch (also known as NOR gate latch),
1. R=HIGH (and S=LOW) a RESET state
S R Q Q'
2. S=HIGH (and R=LOW) a SET state 1 0 1 0 initial
0 0 1 0 (afer S=1, R=0)
3. Both inputs LOW a no change 0 1 0 1
0 0 0 1 (after S=0, R=1)
4. Both inputs HIGH a Q and Q' both LOW (invalid)! 1 1 0 0 invalid!
 Gated D Latch
 Make R input equal to S'  gated D latch.
 D latch eliminates the undesirable condition of invalid state in the S-R latch.
EN D Q(t+1)
D
Q D Q 1 0 0 Reset
EN EN 1 1 1 Set
0 X Q(t) No change
Q' Q'
When EN=1, Q(t+1) = D

 When EN is HIGH,
D=HIGH  latch is SET
D=LOW  latch is RESET

 Hence when EN is HIGH, Q ‘follows’ the D (data) input.

 Characteristic table:
D Flip-flop
• D flip-flop and provide an excitation table and a sample timing
analysis
D CLK
D Q
0  0 1

1  1 0
CLK Q
 : Rising Edge of Clock

• D Flip-Flop: Example Timing

Edge-Triggered Flip-flops
 Flip-flops: synchronous Bistable devices
 Output changes state at a specified point on a triggering input called
the clock.
 Change state either at the positive edge (rising edge) or at the
negative edge (falling edge) of the clock signal.

Clock signal

Positive edges Negative edges

Edge-Triggered Flip-flops
• S-R, D and J-K edge-triggered flip-flops. Note the “>” symbol at the
clock input
S D
Q Q J Q
C
C C
Q' Q' K Q'
R
Positive edge-triggered flip-flops

S D J
Q Q Q
C C C
Q' Q' K Q'
R
Negative edge-triggered flip-flops
S-R Flip-flop
 S-R flip-flop: on the triggering edge of the clock pulse,
S=HIGH (and R=LOW) a SET state
R=HIGH (and S=LOW) a RESET state
both inputs LOW a no change
both inputs HIGH a invalid
 Characteristic table of positive edge-triggered S-R flip-flop:
S R CLK Q(t+1) Comments
0 0 X Q(t) No change
0 1  0 Reset X = irrelevant (“don’t care”)
1 0  1 Set  = clock transition LOW to HIGH
1 1  ? Invalid
S-R Flip-flop
 It comprises 3 parts:
a basic NAND latch
a pulse-steering circuit
a pulse transition detector (or edge detector) circuit
 The pulse transition detector detects a rising (or falling) edge and
produces a very short-duration spike.
 S-R Flip-flop
• The pulse transition detector.
S
Q
Pulse
CLK transition
detector
Q'
R

CLK' CLK'
CLK CLK CLK*
CLK*

CLK CLK

CLK' CLK'

CLK* CLK*

Positive-going transition Negative-going transition

(rising edge) (falling edge)
D Flip-flop
 D flip-flop: single input D (data)
D=HIGH a SET state
D=LOW a RESET state
 Q follows D at the clock edge.
 Convert S-R flip-flop into a D flip-flop: add an inverter
D S D CLK Q(t+1) Comments
Q
C 1  1 Set
CLK
R 0  0 Reset
Q'

A positive edge-triggered D flip-

flop formed with an S-R flip-flop.
J-K Flip-flop
 J-K flip-flop: Q and Q' are fed back to the pulse-steering NAND gates.
 No invalid state. J
Q
Pulse
 Include a toggle state. CLK transition
detector
J=HIGH (and K=LOW) a SET state K
Q'

K=HIGH (and J=LOW) a RESET state

Excitation Table
both inputs LOW a no change
CL Characteristic table
both inputs HIGH a toggle J K
K
J K CLK Q(t+1) Comments
No
0 0  Change 0 0  Q(t) No change
0 1  0 Reset
J Q 0 1  0 Clear 1 0  1 Set

CLK
1 0  1 Set 1 1  Q(t)' Toggle

1 1  Toggle
K Q
 : Rising Edge of Clock
J/K Flip-Flop: Example Timing
Clock Edges
T Flip-flop
• T flip-flop: single-input version of the J-K flip flop, formed by tying
both inputs together
T T J
Q Q
Pulse C
transition CLK
CLK K
detector Q'
Q'

Characteristic table
Q T Q(t+1)
0 0 0
T CLK Q(t+1) Comments
0 1 1
0  Q(t) No change 1 0 1
1  Q(t)' Toggle 1 1 0

Q(t+1) = T.Q' + T'.Q

POS & NEG Edge Triggered D
Positive Edge Trigger

D CLK Q Q
D Q
0  0 1
1  1 0
CLK Q

 : Rising Edge of Clock

Negative Edge Trigger

D CLK Q Q
D Q
0  0 1
1  1 0
CLK Q
 : Falling Edge of Clock
POS & NEG Edge Triggered J/K
Positive Edge Trigger
J K CLK Q
J Q 0 0  Q0
0 1  0
CLK
1 0  1
K Q 1 1  Q0
 : Rising Edge of Clock

Negative Edge Trigger

J K CLK Q
0 0  Q0
J Q
0 1  0
CLK 1 0  1
K Q 1 1  Q0
 : Rising Edge of Clock
Flip-Flop Timing
1
Data Input
(D,J, or K)
0

tS tH
Setup Time Hold Time
Positive 1
Edge
Clock 0

• Setup Time (tS): The time interval before the active transition of the clock signal during
which the data input (D, J, or K) must be maintained.

• Hold Time (tH): The time interval after the active transition of the clock signal during
which the data input (D, J, or K) must be maintained.
Asynchronous Inputs
• Asynchronous inputs (Preset & Clear) are used to override the clock/data inputs
and force the outputs to a predefined state.

• The Preset (PR) input forces the output to:

Q 1 & Q  0 PR

D Q
• The Clear (CLR) input forces the output to:

Q  0 & Q 1 CLK Q
PR CLR CLK D CLR
PRESET CLEAR CLOCK DATA

1 1  0 0 1
1 1  1 1 0
0 1 X X 1 0 Asynchronous Preset
1 0 X X 0 1 Asynchronous Clear
0 0 X X 1 1 ILLEGAL CONDITION
D Flip-Flop: PR & CLR Timing
Transparent D-Latch

EN D Q Q
D Q
0 X Q0 Q0
1 0 0 1
EN Q
1 1 1 0
Transparent D-Latch: Example Timing
Flip-Flop Vs. Latch
• The primary difference between a D flip-flop and D latch is the
EN/CLOCK input.
• The flip-flop’s CLOCK input is edge sensitive, meaning the flip-flop’s
output changes on the edge (rising or falling) of the CLOCK input.
• The latch’s EN input is level sensitive, meaning the latch’s output
changes on the level (high or low) of the EN input.