Lecture # 5

K-Map 5 inputs/Function of Boolean algebra/Encoder-Decoder/ Arithmetic

of Boolean algebra

By: Muhammad Zain Uddin

email: zuddin@iba.edu.pk

M. ZAIN UDDIN 1
Digital Logic Design

Muhammad Zain Uddin

Lecturer,
IBA
Review of previous lecture
Boolean rules Simplification
Designing Rules finalization
K-Maps Rules
K-Map Simplification
3,4 inputs K-map example

M. ZAIN UDDIN 3
Basic Rules of K-Map
A pair can be a combination of means 2,4,8.
A pair can’t be formed diagonally.
We must make largest possible pairs and cover all ones in minimum pairs.
We can make pair of ones with don’t care but its not necessary to cover all don’t care.(we will
cover this in todays lecture)
If a one is left without pair it will be put in our final equation as product form of all inputs (SOP
form) but if a don’t care id left we don’t put that in our equation.

M. ZAIN UDDIN 4
3-variable k Map
◦ Adjacent terms in 3-variable K map.
4-Variable K
Map
 0, 8 are adjacent squares
 0, 2 are adjacent squares, etc.
 1, 4, 13, 7 are adjacent to 5.
 0,8,2,10 are adjacent
Three-Variable K-Maps
f  (0,4) B C f  (4,5) A B f  (0,1,4,5) B f  (0,1,2,3) A

BC BC BC BC
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1

1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0

f  (0,4) A C f  (4,6) A C f  (0,2) A C f  (0,2,4,6) C

BC BC BC BC
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
0 0 1 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1
1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1
Four-Variable K-Maps
CD CD CD CD
00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10
AB AB AB AB
00 0 0 0 0 00 0 0 1 0 00 1 0 1 0 00 0 1 0 1
01 1 1 1 1 01 0 0 1 0 01 0 1 0 1 01 1 0 1 0
11 0 0 0 0 11 0 0 1 0 11 1 0 1 0 11 0 1 0 1

10 0 0 0 0 10 0 0 1 0 10 0 1 0 1 10 1 0 1 0

f  (0, 3,5, 6, 9,10,12,15) f  (1, 2, 4, 7,8,11,13,14)

f   (4,5, 6, 7)  A  B f  (3,7,11,15) C  D
f A  B  C  D f A  B  C  D

CD CD CD CD
00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10
AB AB AB AB
00 0 1 1 0 00 1 0 0 1 00 0 0 0 0 00 1 1 1 1

01 0 1 1 0 01 1 0 0 1 01 1 1 1 1 01 0 0 0 0

11 0 1 1 0 11 1 0 0 1 11 1 1 1 1 11 0 0 0 0

10 0 1 1 0 10 1 0 0 1 10 0 0 0 0 10 1 1 1 1

f  (1, 3,5, 7, 9,11,13,15) f  (0,2,4,6,8,10,12,14) f  (4,5,6,7,12,13,14,15) f  (0,1,2,3,8,9,10,11)

f D f D f B f B
Example of Don’t care
Find the 1 that is covered by only one term first (Do not share with other circle).
5-Variable K
Map
◦ Use two 4-variable map to form a 5-
variable K map (16 + 16 = 32) (A,B,C,D,E)
◦ A’ in the bottom layer
◦ A in the top layer.
 5 Neighbors
Same plane and above or under
Example: 5-variables
Ans: F = A’B’D’ + ABE’ + ACD + A’BCE +
{AB’C or B’CD’}
◦ P1 + P2 + P3 + P4 + AB’C or B’CD’
One More Excample
◦ F = B’C’D’ + B’C’E + A’C’D’ + A’BCD + ABDE +
{C’D’E or AC’E}
◦ (17,19,25,27 =AC’E), (1,9,17,25 = C’D’E)
Decoders
A decoder is a logic circuit that detects the presence of a specific combination of bits at its
input. Two simple decoders that detect the presence of the binary code 0011 are shown. The
first has an active HIGH output; the second has an active LOW output.

A0 A0
A1 X A1 X

A2 A2

A3 A3

Active HIGH decoder for 0011 Active LOW decoder for 0011
Decoders
IC decoders have multiple outputs to decode any combination of inputs. For example the binary-to-
decimal decoder shown here has 16 outputs – one for each combination of binary inputs.

Bin/Dec
0 1
For the input shown, 1 1
2 1
what is the output? 3 1
4 1
1 A0 5 1
6 1
4-bit binary 1 A1 7 1 Decimal
input 0 A2 8 1 outputs
9 1
1 A3 10 1
11 0
12 1
13 1
14 1
15 1
Decoders
X/Y
0
A specific integrated circuit decoder is the
1
74HC154 (shown as a 4-to-16 decoder). It 2
includes two active LOW chip select lines which 3
must be at the active level to enable the 4
outputs. These lines can be used to expand the 5
A0
decoder to larger inputs. A1
1 6
2 7
A2 4 8
A3 8 9
10
11
12
13
14
CS1 & 15
CS2 EN
74HC154
Decoders
BCD/DEC (1)
0
(2)
1
(3)
2
(15) (4)
BCD-to-decimal decoders accept a binary A0 1 3
coded decimal input and activate one of A1 (14) 2 4
(5)
A2 (13) 4 5
(6)
ten possible decimal digit indications. (12)
8 (7)
A3 6
(9)
7
Assume the inputs to the 74HC42 (10)
8
(11)
decoder are the sequence 0101, 9
0110, 0011, and 0010. Describe the
74HC42
output.
All lines are HIGH except for one active output, which is
LOW. The active outputs are 5, 6, 3, and 2 in that order.
BCD Decoder/Driver
Another useful decoder is the 74LS47. This is a BCD-to-seven segment display
with active LOW outputs.
VCC

(16)
BCD/7-seg
The a-g outputs are designed for (4)
BI/RBO BI/RBO
much higher current than most (13)
(7) a
devices (hence the word driver in 1 (12)
(1) b
the name). BCD 2 (11)
(2) c Outputs
inputs 4 (10) to
(6) d
8 (9) seven
e
(3) (15) segmen
LT LT f t device
(5) (14)
RBI RBI g

74LS47 (8)

GND
Truth table
This decoder is built for common
cathode Seven-segment as you can
see we take one as high led and zero
as low.

M. ZAIN UDDIN 19
M. ZAIN UDDIN 20
BCD Decoder/Driver
Here the 7447A is an connected to an LED seven segment display. Notice the
current limiting resistors, required to prevent overdriving the LED display.

+5.0 V
1.0 kW
+5.0 V
74LS47 16
R's = MAN72
BCD/7-seg
3 VCC 330 W 3, 9, 14
LT a 13 1 a
4
BI/RBO b 12 13 b
5 11 10
RBI c c
6 A 10 8
d d
2 B e 9 7 e
BCD
input 1 C f 15 2 f
g 14 11 g
7
D
GND
8
Encoders
An encoder accepts an active logic level on one of its inputs and converts it to
a coded output, such as BCD or binary.

1
The decimal to BCD is an encoder A0
with an input for each of the ten 2

decimal digits and four outputs that 3

A1
represent the BCD code for the
4
active digit. The basic logic diagram 5 A2
6
is shown. There is no zero input 7
because the outputs are all LOW 8
A3
when the input is zero. 9
Encoders
Show how the decimal-to-BCD encoder converts the
decimal number 3 into a BCD 0011.
The top two OR gates have ones as indicated with
the red lines. Thus the output is 0111.

1 0 1
A0
2 0
1
3 1
A1

4 0
5 0 0
0 A2
6 0
7
8 0 0
A3
0
9
Encoders
The 74HC147 is an example of an IC encoder. It is has ten active-LOW inputs
and converts the active input to an active-LOW BCD output.
VCC

(16)
This device is offers additional (11)
HPRI/BCD
1
flexibility in that it is a priority (12)
2
(13)
encoder. This means that if more (1)
3
1
(9)
4 (7)
than one input is active, the one Decimal (2) 5
2
(6)
BCD
input 4 output
with the highest order decimal (3) 6
8
(14)
(4)
digit will be active. (5)
7
8
(10) 9
(8)
74HC147
The next slide shows an application … GND
Half-Adder
Basic rules of binary addition are performed by a
Inputs Outputs
half adder, which has two binary inputs (A and B)
A B Cout S
and two binary outputs (Carry out and Sum). 0 0
0 0
0 1 0 1
The inputs and outputs can be summarized on 1 0 0 1
a truth table. 1 1 1 0

The logic symbol and equivalent circuit are:

S S
A S
A
Cout
B Cout B