Lecture-07:

ARM Assembly Language Programming

Data transfer instructions

15ECE304 Microprocessor and Microcontroller

by
Dr. Ramesh Chinthala
Amrita Vishwa Vidyapeetham, Bengaluru
ARM Assembly Language
Programming
• Data processing instructions
• Data transfer instructions
• Control flow instructions
Data transfer instructions
• Data transfer instructions move data between register(s) and
memory.
• Three basic forms of data transfer instruction in the ARM instruction
set
• Single register load and store instructions
• Multiple register load and store instructions
• Single register swap instructions
Data transfer instructions
• Data transfer instructions move data between transfer and memory.
• Three basic forms of data transfer instruction in the ARM instruction
set
• Single register load and store instructions: LDR, STR
• Multiple register load and store instructions
• Single register swap instructions
Data transfer instructions
• Data transfer instructions move data between transfer and memory.
• Three basic forms of data transfer instruction in the ARM instruction
set
• Single register load and store instructions
• Multiple register load and store instructions: LDM, STM
• Single register swap instructions
Single register load and store
instructions
• LDR R0, [R1] ; R0 = mem32[R1]

• STR R0, [R1] ; mem32[R1] = R0

• Register-indirect addressing uses a value in one register as a memory

address
• This memory address is called base address
• Immediate offset
• Register offset
Initializing an address pointer
COPY ADR R1, LABEL1 ; R1 points to TABEL1
ADR R2, LABEL2 ; R2 points to TABEL2

TABLE1 DATA1 ; source of data

DATA2
……….
DATAN ; destination of data
TABEL2

Here, objective is to transfer data from TABEL1 to TABEL2

Initializing an address pointer
COPY ADR R1, LABEL1 ; R1 points to TABEL1
ADR R2, LABEL2 ; R2 points to TABEL2
LDR R0, [?]

TABLE1 DATA1 ; source of data

DATA2
……….
DATAN ; destination of data
TABEL2

Here, objective is to transfer data from TABEL1 to TABEL2

Initializing an address pointer
COPY ADR R1, LABEL1 ; R1 points to TABEL1
ADR R2, LABEL2 ; R2 points to TABEL2
LDR R0, [?]
SDR R0, [?]

TABLE1 DATA1 ; source of data

DATA2
……….
DATAN ; destination of data
TABEL2

Here, objective is to transfer data from TABEL1 to TABEL2

Initializing an address pointer
COPY ADR R1, LABEL1 ; R1 points to TABEL1
ADR R2, LABEL2 ; R2 points to TABEL2
LDR R0, [R1]
SDR R0, [?]

TABLE1 DATA1 ; source of data

DATA2
……….
DATAN ; destination of data
TABEL2

Here, objective is to transfer data from TABEL1 to TABEL2

Initializing an address pointer
COPY ADR R1, LABEL1 ; R1 points to TABEL1
ADR R2, LABEL2 ; R2 points to TABEL2
LDR R0, [R1]
SDR R0, [R2]

TABLE1 DATA1 ; source of data

DATA2
……….
DATAN ; destination of data
TABEL2

Here, objective is to transfer data from TABEL1 to TABEL2

Initializing an address pointer
COPY ADR R1, LABEL1 ; R1 points to TABEL1
ADR R2, LABEL2 ; R2 points to TABEL2
LDR R0, [R1]
SDR R0, [R2]
ADD
ADD
TABLE1 DATA1 ; source of data
DATA2
……….
DATAN ; destination of data
TABEL2

Here, objective is to transfer data from TABEL1 to TABEL2

Initializing an address pointer
COPY ADR R1, LABEL1 ; R1 points to TABEL1
ADR R2, LABEL2 ; R2 points to TABEL2
LDR R0, [R1]
SDR R0, [R2]
ADD R1, #01
ADD R2, #01
TABLE1 DATA1 ; source of data
DATA2
……….
DATAN ; destination of data
TABEL2

Here, objective is to transfer data from TABEL1 to TABEL2

Initializing an address pointer
COPY ADR R1, LABEL1 ; R1 points to TABEL1
ADR R2, LABEL2 ; R2 points to TABEL2
LDR R0, [R1]
SDR R0, [R2]
ADD R1, #01 ; WRONG
ADD R2, #01 ; WRONG
TABLE1 DATA1 ; source of data
DATA2
……….
DATAN ; destination of data
TABEL2

Here, objective is to transfer data from TABEL1 to TABEL2

Initializing an address pointer
COPY ADR R1, LABEL1 ; R1 points to TABEL1
ADR R2, LABEL2 ; R2 points to TABEL2
LDR R0, [R1]
SDR R0, [R2]
ADD R1, R1, #01
ADD R2, R1, #01
TABLE1 DATA1 ; source of data
DATA2
……….
DATAN ; destination of data
TABEL2

Here, objective is to transfer data from TABEL1 to TABEL2

Initializing an address pointer
COPY ADR R1, LABEL1 ; R1 points to TABEL1
ADR R2, LABEL2 ; R2 points to TABEL2
LDR R0, [R1]
SDR R0, [R2]

TABLE1 DATA1 ; source of data

DATA2
……….
DATAN ; destination of data
TABEL2

Here, objective is to transfer data from TABEL1 to TABEL2

Initializing an address pointer
COPY ADR R1, LABEL1 ; R1 points to TABEL1
ADR R2, LABEL2 ; R2 points to TABEL2
LDR R0, [R1], #01
SDR R0, [R2], #01

TABLE1 DATA1 ; source of data

DATA2
……….
DATAN ; destination of data
TABEL2

Here, objective is to transfer data from TABEL1 to TABEL2

Initializing an address pointer
COPY ADR R1, LABEL1 ; R1 points to TABEL1
ADR R2, LABEL2 ; R2 points to TABEL2
LDR R0, [R1], #01 ; R0 = Mem[R1],
R1 = R1 + 01 means increment the base address in R1 by one and update or store in R1
SDR R0, [R2], #01 ; POST INDEXING ADDRESSING MODE

TABLE1 DATA1 ; source of data

DATA2
……….
DATAN ; destination of data
TABEL2

Here, objective is to transfer data from TABEL1 to TABEL2

Base plus off-set addressing
• LDR R0, [R1, #04]

• LDR R0, [R1, #04]!

• LDR R0, [R1], #04

•?
Base plus off-set addressing
• LDR R0, [R1, #04]; R0 = mem32[R1+4]

• LDR R0, [R1, #04]!; R0 = mem32[R1+4]

R1 = R1 + 4

• LDR R0, [R1], #04; R0 = mem32[R1]

R1 = R1 + 4
•?
Base plus off-set addressing
• LDR R0, [R1, #04]; R0 = mem32[R1+4]
• Pre-indexing means pre-increment the address pointer then transfer

• LDR R0, [R1, #04]!; R0 = mem32[R1+4]

R1 = R1 + 4

• LDR R0, [R1], #04; R0 = mem32[R1]

R1 = R1 + 4
•?
Base plus off-set addressing
• LDR R0, [R1, #04]; R0 = mem32[R1+4]
• Pre-indexing

• LDR R0, [R1, #04]!; R0 = mem32[R1+4]

R1 = R1 + 4
• Auto indexing means pre-increment address pointer then transfer, and update the
pointer

• LDR R0, [R1], #04; R0 = mem32[R1]

R1 = R1 + 4
•?
Base plus off-set addressing
• LDR R0, [R1, #04]; R0 = mem32[R1+4]
• Pre-indexing

• LDR R0, [R1, #04]!; R0 = mem32[R1+4]

R1 = R1 + 4
• Auto indexing

• LDR R0, [R1], #04; R0 = mem32[R1]

R1 = R1 + 4
• Post indexing means transfer first then increment the address pointer
Single-register Data Transfer
• Most flexible way to transfer single data items b/w ARM and memory
• Data item
• May be a 32-bit word LDR R0, [R1]; R0 = Mem[R1][31:0]
• May be a 16-bit half-word LDR R0, [R1]
• May be a 08-bit byte LDRB R0, [R1]

• May be a 32-bit word STR R0, [R1]

• May be a 16-bit half-word STR R0, [R1]
• May be a 08-bit byte STRB R0, [R1]
Single-register Data Transfer
• Most flexible way to transfer single data items b/w ARM and memory
• Data item
• May be a 32-bit word LDR R0, [R1]; R0 = Mem[R1][31:0]
• May be a 16-bit half-word LDR R0, [R1]; R0 = Mem[R1][15:0]
• May be a 08-bit byte LDRB R0, [R1]

• May be a 32-bit word STR R0, [R1]

• May be a 16-bit half-word STR R0, [R1]
• May be a 08-bit byte STRB R0, [R1]
Single-register Data Transfer
• Most flexible way to transfer single data items b/w ARM and memory
• Data item
• May be a 32-bit word LDR R0, [R1]; R0 = Mem[R1][31:0]
• May be a 16-bit half-word LDR R0, [R1]; R0 = Mem[R1][15:0]
• May be a 08-bit byte LDRB R0, [R1]; R0 = Mem[R1][7:0]

• May be a 32-bit word STR R0, [R1]

• May be a 16-bit half-word STR R0, [R1]
• May be a 08-bit byte STRB R0, [R1]
Single-register Data Transfer
• Most flexible way to transfer single data items b/w ARM and memory
• Data item
• May be a 32-bit word LDR R0, [R1]; R0 = Mem[R1][31:0]
• May be a 16-bit half-word LDR R0, [R1]; R0 = Mem[R1][15:0]
• May be a 08-bit byte LDRB R0, [R1]; R0 = Mem[R1][7:0]

• May be a 32-bit word STR R0, [R1]; Mem[R1][31:0] = R0

• May be a 16-bit half-word STR R0, [R1]
• May be a 08-bit byte STRB R0, [R1]
Single-register Data Transfer
• Most flexible way to transfer single data items b/w ARM and memory
• Data item
• May be a 32-bit word LDR R0, [R1]; R0 = Mem[R1][31:0]
• May be a 16-bit half-word LDR R0, [R1]; R0 = Mem[R1][15:0]
• May be a 08-bit byte LDRB R0, [R1]; R0 = Mem[R1][7:0]

• May be a 32-bit word STR R0, [R1]; Mem[R1][31:0] = R0

• May be a 16-bit half-word STR R0, [R1]; Mem[R1][16:0] = R0
• May be a 08-bit byte STRB R0, [R1]
Single-register Data Transfer
• Most flexible way to transfer single data items b/w ARM and memory
• Data item
• May be a 32-bit word LDR R0, [R1]; R0 = Mem[R1][31:0]
• May be a 16-bit half-word LDR R0, [R1]; R0 = Mem[R1][15:0]
• May be a 08-bit byte LDRB R0, [R1]; R0 = Mem[R1][7:0]

• May be a 32-bit word STR R0, [R1]; Mem[R1][31:0] = R0

• May be a 16-bit half-word STR R0, [R1]; Mem[R1][16:0] = R0
• May be a 08-bit byte STRB R0, [R1]; Mem[R1][7:0] = R0
Single-register Data Transfer
• Most flexible? way to transfer single data items b/w ARM and memory
• Data item
• May be a 32-bit word LDR R0, [R1]; R0 = Mem[R1][31:0]
• May be a 16-bit half-word LDR R0, [R1]; R0 = Mem[R1][15:0]
• May be a 08-bit byte LDRB R0, [R1]; R0 = Mem[R1][7:0]

• May be a 32-bit word STR R0, [R1]; Mem[R1][31:0] = R0

• May be a 16-bit half-word STR R0, [R1]; Mem[R1][16:0] = R0
• May be a 08-bit byte STRB R0, [R1]; Mem[R1][7:0] = R0
Multiple-register Data Transfer
• LDR R0, [R1]
• LDM R0, [R1]
• LDM R1, {R2-R3}

• STR R0, [R1]

• STM R0, [R1]
• STM R1, {R2-R3}
Multiple-register Data Transfer
• LDR R0, [R1]
• LDM R0, [R1] wrong
• LDM R1, {R1-R3}

• STR R0, [R1]

• STM R0, [R1]
• STM R1, {R2-R3}
Multiple-register Data Transfer
• LDR R0, [R1]
• LDM R0, [R1] wrong
• LDM R1, {R1-R3} correct

• STR R0, [R1]

• STM R0, [R1]
• STM R1, {R2-R3}
Multiple-register Data Transfer
• LDR R0, [R1]
• LDM R0, [R1] wrong
• LDM R1, {R1-R3} correct

• STR R0, [R1]

• STM R0, [R1] wrong
• STM R1, {R2-R3}
Multiple-register Data Transfer
• LDR R0, [R1]
• LDM R0, [R1] wrong
• LDM R1, {R1-R3} correct

• STR R0, [R1]

• STM R0, [R1] wrong
• STM R1, {R2-R3} correct
Multiple-register Data Transfer
• Less flexible but transfers multiple data items b/w ARM and memory
• Data items are 32-bit words
• LDM R0, {R1-R3}; R1 = Mem[R1][31:0]
R2 = Mem[R1][31:0]
R3 = Mem[R1][31:0]

• STM R0, {R1-R3}; Mem[R0][31:0] = R1

Mem[R0][31:0] = R2
Mem[R0][31:0] = R3
Multiple-register Data Transfer
• Less flexible but transfers multiple data items b/w ARM and memory
• Data items are 32-bit words
• LDM R0, {R1-R3}; R1 = Mem[R1][31:0]
R2 = Mem[R1][31:0]
R3 = Mem[R1][31:0]

• STM R0, {R1-R3}; Mem[R0][31:0] = R1

Mem[R0][31:0] = R2
Mem[R0][31:0] = R3
Multiple-register Data Transfer
• Less flexible but transfers multiple data items b/w ARM and memory
• Data items are 32-bit words
• LDM R0, {R1-R3}; R1 = Mem[R1+0][31:0]
R2 = Mem[R1+4][31:0]
R3 = Mem[R1+8][31:0]

• STM R0, {R1-R3}; Mem[R0+0][31:0] = R1

Mem[R0+4][31:0] = R2
Mem[R0+8][31:0] = R3
Multiple-register Data Transfer
• Less flexible but transfers multiple data items b/w ARM and memory
• Data items are 32-bit words
• LDM R0, {R1-R3}; R1 = Mem[R1+0][31:0]
R2 = Mem[R1+4][31:0]
R3 = Mem[R1+8][31:0]

• STM R0, {R1-R3}; Mem[R0+0][31:0] = R1

Mem[R0+4][31:0] = R2
Mem[R0+8][31:0] = R3
Multiple-register Data Transfer
• Less flexible but transfers multiple data items b/w ARM and memory
• Data items are 32-bit words
• LDM R0, {R1-R3}; R1 = Mem[R1+0][31:0]
R2 = Mem[R1+4][31:0]
R3 = Mem[R1+8][31:0]

• STM R0, {R1-R3}; Mem[R0+0][31:0] = R1

Mem[R0+4][31:0] = R2
Mem[R0+8][31:0] = R3
Multiple-register Data Transfer
• Less flexible but transfers multiple data items b/w ARM and memory
• Data items are 32-bit words
• LDM R0, {R1-R3}; R1 = Mem[R1+0][31:0]
R2 = Mem[R1+4][31:0]
R3 = Mem[R1+8][31:0]

• STM R0, {R1-R3}; Mem[R0+0][31:0] = R1

Mem[R0+4][31:0] = R2
Mem[R0+8][31:0] = R3
Multiple-register Data Transfer
• Less flexible but transfers multiple data items b/w ARM and memory
• Data items are 32-bit words
• LDM R0, {R1-R3}; R1 = Mem[R1+0][31:0]
R2 = Mem[R1+4][31:0]
R3 = Mem[R1+8][31:0]

• STM R0, {R1-R3}; Mem[R0+0][31:0] = R1

Mem[R0+4][31:0] = R2
Mem[R0+8][31:0] = R3
Single register swap instruction
• Swap a value in a register with a value in memory
• Little used in ULP
• To implement semaphores to ensure mutual exclusions on accesses
to shared data structures in multiprocessor systems
Thank You