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WINSEM2024-25_BCSE205L_TH_VL2024250501432_2024-12-18_Reference-Material-I

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9 views21 pages

WINSEM2024-25_BCSE205L_TH_VL2024250501432_2024-12-18_Reference-Material-I

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nukalasairam2023
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Cont’d

• (logical) The interface of an I/O device includes a control register that contains the
information that governs the mode of operation of the device.
• One bit in this register may be dedicated to interrupt control
• The I/O device is allowed to raise interrupt requests only when this bit is set to 1
• What is relation between Status register and Control register?
• The information needed to determine whether a device is requesting an interrupt is available
in its status register
• When the device raises an interrupt request, it sets to 1 a bit in its status register, which we
will call the IRQ bit
• The simplest way to identify the interrupting device is to have the interrupt-service routine
poll all I/O devices in the system
• The first device encountered with its IRQ bit set to 1 is the device that should be serviced
• An appropriate subroutine is then called to provide the requested service
How are the functional units connected?
•For a computer to achieve its operation, the functional units need to
communicate with each other.
•In order to communicate, they need to be connected.

Input Output Memory Processor

Bus

•Functional units may be connected by a group of parallel wires.


•The group of parallel wires is called a bus.
•Each wire in a bus can transfer one bit of information.
•The number of parallel wires in a bus is equal to the word length of
a computer

2
Organization of cache and main
memory
Main Cache
memory memory Processor

Bus

Why is the access time of the cache memory lesser than the
access time of the main memory?

3
Computer Components: Top-Level View
Basic Operational Concepts
A Partial Program Execution Example
A Partial Program Execution Example
Interrupt

• Normal execution of programs may be interrupted if


some device requires urgent servicing
• To deal with the situation immediately, the normal execution of the current
program must be interrupted

• Procedure of interrupt operation


• The device raises an interrupt signal
• The processor provides the requested service by executing an appropriate
interrupt-service routine
• The state of the processor is first saved before servicing the interrupt
• Normally, the contents of the PC, the general registers, and some control
information are stored in memory
• When the interrupt-service routine is completed, the state of the processor is
restored so that the interrupted program may continue
Cont’d
• The PC contains 300, the address of the first instruction. The instruction (the value 1940 in
hex) is loaded into IR and PC is incremented. This process involves the use of MAR and
MBR.
• The first hexadecimal digit in IR indicates that the AC is to be loaded. The remaining three
hexadecimal digits specify the address (940) from which data are to be loaded.
• The next instruction (5941) is fetched from location 301 and PC is incremented.
• The old contents of AC and the contents of location 941 are added and the result is stored in
the AC.
• The next instruction (2941) is fetched from location 3
Classes of Interrupts

• Program
• Generated by some condition that occurs as a result of an
instruction execution such as arithmetic overflow, division by
zero, attempt to execute an illegal machine instruction, or
reference outside a user’s allowed memory space
• Timer
• Generated by a timer within the processor. This allows the
operating system to perform certain functions on a regular basis
• I/O
• Generated by an I/O controller, to signal normal completion of
an operation or to signal a variety of error conditions
• Hardware failure
• Generated by a failure such as power failure or memory parity
error
Bus Structures

• A group of lines that serves a connecting path for several devices is


called a bus
• In addition to the lines that carry the data, the bus must
have lines for address and control purposes
• The simplest way to interconnect functional units is to use
a single bus, as shown below
Drawbacks of the Single Bus Structure

• The devices connected to a bus vary widely in their speed


of operation
• Some devices are relatively slow, such as printer and keyboard
• Some devices are considerably fast, such as optical disks
• Memory and processor units operate are the fastest parts of a
computer
• Efficient transfer mechanism thus is needed to cope with
this problem
• A common approach is to include buffer registers with the
devices to hold the information during transfers
• Another approach is to use two-bus structure and an additional
transfer mechanism
• A high-performance bus, a low-performance, and a bridge for
transferring the data between the two buses. ARMA Bus belongs to this
structure
Software
• In order for a user to enter and run an application program, the
computer must already contain some system software in its memory

• System software is a collection of programs that are executed as


needed to perform functions such as
• Receiving and interpreting user commands
• Running standard application programs such as word processors,
etc, or games
• Managing the storage and retrieval of files in secondary storage
devices
• Controlling I/O units to receive input information and produce
output results
Software

• Translating programs from source form prepared by the user into object form consisting
of machine instructions

• Linking and running user-written application programs with existing standard library
routines, such as numerical computation packages

• System software is thus responsible for the coordination of all activities in a computing
system
Operating System

• Operating system (OS)


• This is a large program, or actually a collection of routines, that is
used to control the sharing of and interaction among various
computer units as they perform application programs
• The OS routines perform the tasks required to assign
computer resource to individual application programs
• These tasks include assigning memory and magnetic disk space to
program and data files, moving data between memory and disk
units, and handling I/O operations
• In the following, a system with one processor, one disk, and
one printer is given to explain the basics of OS
• Assume that part of the program’s task involves reading a data file
from the disk into the memory, performing some computation on
the data, and printing the results
User Program and OS Routine Sharing
Multiprogramming or Multitasking
Performance

• The speed with which a computer executes programs


is affected by the design of its hardware and its
machine language instructions

• Because programs are usually written in a high-level


language, performance is also affected by the
compiler that translates programs into machine
languages

• For best performance, the following factors must be


considered
• Compiler
• Instruction set
Performance
• Processor circuits are controlled by a timing signal
called a clock
• The clock defines regular time intervals, called clock cycles
• To execute a machine instruction, the processor
divides the action to be performed into a sequence of
basic steps, such that each step can be completed in
one clock cycle
• Let the length P of one clock cycle, its inverse is the
clock rate, R=1/P
• Basic performance equation
• T=(NxS)/R, where T is the processor time required to
execute a program, N is the number of instruction
executions, and S is the average number of basic steps
Performance Improvement

• Pipelining and superscalar operation


• Pipelining: by overlapping the execution of successive
instructions
• Superscalar: different instructions are concurrently
executed with multiple instruction pipelines. This means
that multiple functional units are needed
• Clock rate improvement
• Improving the integrated-circuit technology makes
logic circuits faster, which reduces the time needed to
complete a basic step
Performance Improvement

• Reducing amount of processing done in one basic step also makes it


possible to reduce the clock period, P.
• However, if the actions that have to be performed by an instruction
remain the same, the number of basic steps needed may increase
• Reduce the number of basic steps to execute
• Reduced instruction set computers (RISC) and complex instruction set
computers (CISC)

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