Scribd
Upload
8 views24 pages

Computer Archtiecture Lec 1

The document outlines the key concepts in computer architecture, including definitions, register transfer language (RTL), microoperations, and memory transfer. It discusses the modular approach and various logic types, as well as the motivation for common bus systems. Additionally, it includes references and mentions assignments and quizzes related to the material covered.

Uploaded by

aalhuseiny
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
Download as pptx, pdf, or txt
8 views24 pages

Computer Archtiecture Lec 1

The document outlines the key concepts in computer architecture, including definitions, register transfer language (RTL), microoperations, and memory transfer. It discusses the modular approach and various logic types, as well as the motivation for common bus systems. Additionally, it includes references and mentions assignments and quizzes related to the material covered.

Uploaded by

aalhuseiny
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
Download as pptx, pdf, or txt
Download as pptx, pdf, or txt
You are on page 1/ 24

Computer

Architecture
ABET Compliant
Ahmed Alhuseiny
Lec. 1 – Ch4
Make sure you followed and
stick to…

2
Outline
• Introduction
• Definitions
• Register Transfer Language (RTL)
• Register Transfer
• Bus & Memory Transfer
• Arithmetic Microoperation
• Logic Microoperation
• Shift Microoperation
• Arithmetic Logic Unit
• Reading ch4 from the textbook
3
Computer Organization and Computer
Architecture? Archi or Orga is first?

4
Definitions
• Modular Approach
• PCB, Resistor–transistor logic (RTL)
• IC, Emitter-coupled logic (ECL)
• SSI Diode–transistor logic (DTL)
• LSI Metal–oxide–semiconductor (MOS) logic
• VLSI Integrated injection logic (I2L)
• ULSI Gunning transceiver logic (GTL)
• WSI
• 5
Microoperations, RTL and RT

6
Microoperations, RTL and RT

7
RTL Rules

8
Microoperations, RTL and RT

9
Microoperations, RTL and RT

P is active here only!

10
Motivation for Common Bus

# Connections = n Reg (n Reg -1). It’s almost like Full Mesh Topology
11
Common Bus using MUXs
1
0

12
Common Bus using Tri-State
Buffer

10
13
Common Bus using Tri-State
Buffer

1
1
1
14
Reconfiguring Fig 4.3 by Tri-State
Buffer

Labels should be A0, A1, A2, A3 and so on for other


corresponding Registers nd one decoder is adequate to control
all buffers; however, here we fan out of decoders is low. If
mentioned high fan out, so one decoder is enough!!!

15
Memory Transfer

16
Memory Transfer
Read: DR  M[AR]

17
Memory Transfer
: M[AR]  DR

18
Memory Transfer
List the Microoperations to transfer data from a computer register to Memory.
Suppose compute register is R1.
Memory location is at AR register.
Memory only transfer to/ from DR
So the microoperations would be like
DR R1

M[AR]  DR

19
Memory Transfer
List the Microoperations to transfer data from Memory to a computer register.

20
Hw1

It is posted on the classroom.

21
Quiz
What is the number of
connections to achieve fully
meshed connections if you have
n registers and if you have (n-1)
registers?
22
References:
M. M. Mano, Computer System Architecture (3rd Ed.).
USA: Prentice-Hall, Inc., 1993.

Other Online resources.


24

You might also like