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USC, Information Sciences Institiute
- Tucson, Arizona, USA
- http://www.reynwar.net/ben
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SiLemma Public
Trying to prove things about circuits in Dafny
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VossII Public
Forked from TeamVoss/VossIIThe source code to the Voss II Hardware Verification Suite
Verilog Apache License 2.0 UpdatedApr 10, 2024 -
slvcodec Public
Generate conversions to/from VHDL types and std_logic_vector. Generate python-based tests.
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openpiton Public
Forked from PrincetonUniversity/openpitonThe OpenPiton Platform
Assembly UpdatedDec 19, 2023 -
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verilog-axi Public
Forked from alexforencich/verilog-axiVerilog AXI components for FPGA implementation
Verilog MIT License UpdatedMar 1, 2023 -
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silveroak Public
Forked from project-oak/silveroakFormal specification and verification of hardware, especially for security and privacy.
Coq Apache License 2.0 UpdatedMay 19, 2022 -
cocotb-test Public
Forked from themperek/cocotb-testUnit testing for cocotb
Python BSD 2-Clause "Simplified" License UpdatedApr 21, 2022 -
cephalopode Public
Forked from dlesbre/cephalopodeThe cephalopod IoT processor and the bifrost compiler
Haskell Apache License 2.0 UpdatedFeb 4, 2022 -
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latte21 Public
Forked from cucapra/latte21Languages, Tools, and Techniques for Accelerator Design
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fusesoc Public
Forked from olofk/fusesocFuseSoC is a package manager and a set of build tools for FPGA/ASIC development
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VHDL 2008/93/87 simulator
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check_cocotb_ghdl Public
Just a check to make sure cocotb and ghdl are working together
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cocotb Public
Forked from cocotb/cocotbCoroutine Co-simulation Test Bench
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edalize Public
Forked from olofk/edalizeAn abstraction library for interfacing EDA tools
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CoSA Public
Forked from cristian-mattarei/CoSACoreIR Symbolic Analyzer
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vunit Public
Forked from VUnit/vunitVUnit is a unit testing framework for VHDL/SystemVerilog
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nmigen Public
Forked from m-labs/nmigenA refreshed Python toolbox for building complex digital hardware
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cocotb-testrunner Public
Forked from imphil/cocotb-testrunnerRun tests with cocotb
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fusesoc_generators Public
Add generators to fusesoc so that depenedencies can be generated from generic parameters.
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symbiflow-arch-defs Public
Forked from f4pga/f4pga-arch-defsFOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
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vtr-verilog-to-routing Public
Forked from verilog-to-routing/vtr-verilog-to-routingVerilog to Routing -- Open Source CAD Flow for FPGA Research