topaz

An out-of-order, single issue processor for the LC3-b ISA

This code was developed for the final project for ECE 411 - Computer Organization and Design at UIUC. I wrote it with group partners Neil Singh and Saurav Puri. Some code was provided by course instructors.

The processor is based on the traditional Tomasulo out-of-order design. There is a functioning branch predictor. There is a two-level cache but it had several bugs at the end of development.

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
BTB.sv		BTB.sv
LICENSE		LICENSE
README.md		README.md
adj.sv		adj.sv
agu.sv		agu.sv
agu_rs.sv		agu_rs.sv
alu.sv		alu.sv
alu_rs.sv		alu_rs.sv
and2input.sv		and2input.sv
and3input.sv		and3input.sv
arbiter.sv		arbiter.sv
arbiter_control.sv		arbiter_control.sv
arbiter_datapath.sv		arbiter_datapath.sv
array.sv		array.sv
branch_predictor.sv		branch_predictor.sv
control.sv		control.sv
control_flow_rs.sv		control_flow_rs.sv
cpu_datapath.sv		cpu_datapath.sv
cpu_decode.sv		cpu_decode.sv
cpu_fetch.sv		cpu_fetch.sv
datapath.sv		datapath.sv
decoder.sv		decoder.sv
demux2_1.sv		demux2_1.sv
eight-eightconcat.sv		eight-eightconcat.sv
gencc.sv		gencc.sv
iqueue.sv		iqueue.sv
ir.sv		ir.sv
l1cache_datapath.sv		l1cache_datapath.sv
l1dcache.sv		l1dcache.sv
l1dcache_control.sv		l1dcache_control.sv
l1icache.sv		l1icache.sv
l1icache_control.sv		l1icache_control.sv
l2cache.sv		l2cache.sv
l2cache_control.sv		l2cache_control.sv
l2cache_datapath.sv		l2cache_datapath.sv
lc3b_types.sv		lc3b_types.sv
loadstore_queue.sv		loadstore_queue.sv
macros.sv		macros.sv
magic_memory.sv		magic_memory.sv
magic_memory_dp.sv		magic_memory_dp.sv
mp3.out.sdc		mp3.out.sdc
mp3.qpf		mp3.qpf
mp3.qsf		mp3.qsf
mp3.sv		mp3.sv
mp3_tb.sv		mp3_tb.sv
mux2.sv		mux2.sv
mux3.sv		mux3.sv
mux4.sv		mux4.sv
mux8.sv		mux8.sv
or2input.sv		or2input.sv
or4input.sv		or4input.sv
physical_memory.sv		physical_memory.sv
plus2.sv		plus2.sv
pseudolru.sv		pseudolru.sv
regfile.sv		regfile.sv
register.sv		register.sv
rename.sv		rename.sv
reorder_buffer.sv		reorder_buffer.sv
res_arbitrator.sv		res_arbitrator.sv
reservation_station.sv		reservation_station.sv
sixteen-onetwentyeightconcat.sv		sixteen-onetwentyeightconcat.sv
slow_lsq.sv		slow_lsq.sv
tag_comp.sv		tag_comp.sv

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