Ibex ASCON Extension

Extending the Instruction Set Of RISC-V Processor for ASCON Algorithm.

Running the processor

The project runs on only Vivado 2018.1 and its simulator, I never tried on any FPGA board and other simulators.

Open the lowrisc_ibex_top_artya7_100_0.1.xpr file in the modified_ibex/build/lowrisc_ibex_top_artya7_100_0.1/synth-vivado directory.
Modify the 65th line of the ram_1p.sv file to load your memory files.
Run the simulator.

To compile programs for the processor:

cd sw
make

Change Makefile for advanced compiling options.

Name		Name	Last commit message	Last commit date
Latest commit History 13 Commits
modified_ibex		modified_ibex
sw		sw
Extending the Instruction Set of RISC-V Processor for ASCON Algorithm.pdf		Extending the Instruction Set of RISC-V Processor for ASCON Algorithm.pdf
README.md		README.md