GitHub - jncraton/MIPS-Lite: A pipelined MIPS-Lite CPU implementation

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 47 Commits
ALU.vhdl		ALU.vhdl
ALUControl.vhdl		ALUControl.vhdl
ALUControl_tb.vhdl		ALUControl_tb.vhdl
ALU_tb.vhdl		ALU_tb.vhdl
CPU.vhdl		CPU.vhdl
Execute.vhdl		Execute.vhdl
ForwardComparator.vhdl		ForwardComparator.vhdl
ForwardControl.vhdl		ForwardControl.vhdl
ForwardControl_tb.vhdl		ForwardControl_tb.vhdl
IF.vhdl		IF.vhdl
InstructionDecode.vhdl		InstructionDecode.vhdl
InstructionFetch.vhdl		InstructionFetch.vhdl
Memory.vhdl		Memory.vhdl
PipelineRegister.vhdl		PipelineRegister.vhdl
RegFile.vhdl		RegFile.vhdl
RegFile_tb.vhdl		RegFile_tb.vhdl
Register_EX_MEM.vhdl		Register_EX_MEM.vhdl
Register_ID_EX.vhdl		Register_ID_EX.vhdl
Register_IF_ID.vhdl		Register_IF_ID.vhdl
Register_MEM_WB.vhdl		Register_MEM_WB.vhdl
Writeback.vhdl		Writeback.vhdl
adder.vhdl		adder.vhdl
adder32.vhdl		adder32.vhdl
adder32_tb.vhdl		adder32_tb.vhdl
adder_tb.vhdl		adder_tb.vhdl
asm.pl		asm.pl
build.pl		build.pl
code.asm		code.asm
comparator.vhdl		comparator.vhdl
control.vhdl		control.vhdl
control_tb.vhdl		control_tb.vhdl
decoder1to2.vhdl		decoder1to2.vhdl
decoder1to2_tb.vhdl		decoder1to2_tb.vhdl
decoder2to4.vhdl		decoder2to4.vhdl
decoder2to4_tb.vhdl		decoder2to4_tb.vhdl
decoder4to16.vhdl		decoder4to16.vhdl
decoder4to16_tb.vhdl		decoder4to16_tb.vhdl
decoder5to32.vhdl		decoder5to32.vhdl
decoder5to32_tb.vhdl		decoder5to32_tb.vhdl
dff.vhdl		dff.vhdl
gate_and.vhdl		gate_and.vhdl
gate_not.vhdl		gate_not.vhdl
gate_or.vhdl		gate_or.vhdl
gate_xor.vhdl		gate_xor.vhdl
gen_tb.pl		gen_tb.pl
logical_not.vhdl		logical_not.vhdl
lshift32.vhdl		lshift32.vhdl
lshift32_tb.vhdl		lshift32_tb.vhdl
memory.dat		memory.dat
mux16to1.vhdl		mux16to1.vhdl
mux2to1.vhdl		mux2to1.vhdl
mux2to1_indiv.vhdl		mux2to1_indiv.vhdl
mux2to1_tb.vhdl		mux2to1_tb.vhdl
mux32to1.vhdl		mux32to1.vhdl
mux32to1_tb.vhdl		mux32to1_tb.vhdl
mux4to1.vhdl		mux4to1.vhdl
mux4to1_indiv.vhdl		mux4to1_indiv.vhdl
mux4to1_tb.vhdl		mux4to1_tb.vhdl
readme.txt		readme.txt
register1.vhdl		register1.vhdl
register2.vhdl		register2.vhdl
register3.vhdl		register3.vhdl
register32.vhdl		register32.vhdl
register4.vhdl		register4.vhdl
register5.vhdl		register5.vhdl
register6.vhdl		register6.vhdl
rshift.vhdl		rshift.vhdl
rshift32_tb.vhdl		rshift32_tb.vhdl
sram-tb.vhdl		sram-tb.vhdl
sram.vhdl		sram.vhdl
txt_util.vhdl		txt_util.vhdl

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This is my pipelined CPU implementation.

The main entity is located in CPU.vhdl. It is divided into entities by 
stage. Each stage has its own entity and its own register to store the 
state.

My implementation uses forwarding to handle data hazards.

I created an assembler (asm.pl) which converts the assembly in code.asm 
to machine code and stores it in memory.dat.

The current memory.dat file contains the machine code for the current 
code.asm file. My CPU contains a process which performs testing on the 
CPU. This is not currently active, but it can be activated by changing 
a false to a true. In order for this testing to succeed, the CPU needs 
to be running the code in memory.dat.

This code is also available on github: http://github.com/jncraton/MIPS-Lite