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Directory-based-cache
Directory-based-cache PublicForked from harsha1304/Directory-based-cache
This repository contains a synthesizable Verilog code for L1 cache and Directory +L2 cache. The project is done as part of the course work VLSI Design Laboratory at University of Minnesota - Twin c…
Verilog
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Pytorch-UNet
Pytorch-UNet PublicForked from milesial/Pytorch-UNet
PyTorch implementation of the U-Net for image semantic segmentation with high quality images
Python
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extra-benchmark
extra-benchmark PublicThe extra benchmarks of paper "ADSAPlace:Alignment-Driven Simulated Annealing for PCB Placement"
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