RISC-V Devicetrees for v6.20

Sophgo:

For CV18xx serials:
Update RX/TX FIFO size to fix the USB transfer issue.

For SG2042:
Optimize the DTS file format, including moving PLIC/CLINT
nodes into cpu dtsi and sorting peripheral nodes by address.
In addition, we also enable RTC for Pioneerbox.

For SG2044:
Add "b" ISA extension to fix dtbs_check warnings.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

RISC-V Devicetrees for v6.19

Sophgo:

For CV18xx serials:
Add top syscon device related DTS change, the top system
controller provides register access to configure some
misc modules, such as usb2 phy and a dma multiplexer.

For SG2042:
There are two changes. The first one is to add DTS
definition for PCIe controllers for SoC SG2042 and
boards such as Pioneerbox/EVB_V1/EVB_V2 uses SG2042.
The second one is to add DTS to support SPI-NOR flash
controllers for this SoC and the same for related boards.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

RISC-V Devicetrees for v6.18

Sophgo:

Minor changes here only for SG2042. Enable numa
and we can see significant performance improvements,
for example in the STREAM test.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

RISC-V Devicetrees for v6.17

Sophgo:

For CV18xx serials:
There are three major changes. The first is to add the
RTCSYS MFD node, which provides rich control registers
for soc power management and other rich control functions;
the second is to add the reset controller node and add
related reset properties for other peripherals; the third
is to add ethernet controller related nodes to the soc
and enable ethernet device control for HuashanPi.

For SG2042:
There are three major changes. The first is to add ISA
extensions such as xtheadvector/ziccrse/zfh for cpu cores;
the second is add ethernet controller support; the third
is add two new boards EVB_V1 & EVB_V2 which use SG2042
SoC.

For SG2044:
There are many changes. The first is to add pmu
configuration; the second is to add ISA extensions
ziccrse and add missing riscv,cbop-block-size property
for cpu cores; the third is to add more peripherals
nodes for SoC after clock controller is ready, such as
MSI/PCIe/pwm/SPI-NOR etc. This PR also add HWMON MCU
device for the sophgo-srd3-10 board and reserve uart0
node for sophgo-srd3-10 board because uart0 is already
occupied by the firmware.

This PR also moves sophgo.yaml from the riscv directory
to soc/sophgo for sharing between riscv and arm. CV18xx
SoC contains a RISC-V big core and an ARM64 big core.
Moving sophgo.yaml to a shared location will help us
add support for ARM cores to the CV18xx chip in the future.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

ARM Devicetrees for v6.17

Sophgo:

Add support for Duo Module 01 Evaluation Board.
This board uses SG2000(old codename CV181xH),
which is dual-arch, RISC-V and ARM64. This
patch add the support for ARM64.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

RISC-V Devicetrees for v6.16

Sophgo:
Add Pinctrl & SPI support for SG2042 SoC, and
refactor the dts of cv18xx to facilitate adding
support for arm core later (SG200X has two cores,
one is RISC-V and another is ARM64).
Also add initial support for Sophgo SG2044/SRD3-10.
SRD3-10 board bases on Sophgo SG2044 SoC and
initial support includes uart only. This part of
the changes involves some modifications to dts
and bindings.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

RISC-V SoC for v6.16

Sophgo:

Add support for SG2044 TOP syscon device. The SG2044 TOP
device provide PLL clock function in its area.

Add RTC support for CV1800 series SoC. The device
is called RTC, but contains control registers of other
HW blocks in its address space, most notably of
Power-on-Reset (PoR) module, DW8051 IP (MCU core),
accompanying SRAM, hence putting it in SoC subsystem.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

RISC-V Sophgo clock driver changes for v6.16

Sophgo:
Replace compatible for CV1800 series SoC.
Add clock support for SG2044.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>

RISC-V Sophgo Devicetree fixes for v6.15-rc1

Just one minor fix to correct DMA data-width
configuration for CV18xx.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

RISC-V Devicetrees for v6.15

Sophgo:
Add pwm controller support for SG2042.
Add pwm-fan & cooling maps for Milk-V Pioneer.
Updated MAINTAINERS info for SOPHGO DEVICETREES and DRIVERS.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>