VLSI Design Tools
Design Flow
Design Details
Code Editors/Doc
Editors
FrontEnd
Simulation
Debug
Lint Checking
Equivalence Checking
Coverage
Formal Verification
SV Verification
Tools
Company
Vi/Vim
GNU
Emacs
GNU
FrameMake
Adobe
Office
Microsoft
VCS
Synopsys
NC-Verilog(IUS)
Cadence
Verilog XL
Cadence
ModelSim
Mentor
Debussy
SpringSoft/Novas
Verdi
SpringSoft/Novas
Simvision
Cadence
DVE
Synopsys
HAL
Cadence
SpyGlass
Atrenta
0-in Checklist
Archer
nLint
SpringSoft/Novas
LEC
Cadence/Verplex
Conformal ASIC
Cadence
SLV
Cadence
HDLScore
Summit
ICC
Cadence
InfiniteStream
Cacence
VCS Coverage Metrics
Synopsys
Fromality
Synopsys
BlackTie
Cadence/Verplex
IFV
Cadence
Open Vera
Synopsys
Specman Elite
Verisity
VCS/SystemVerilog
Synopsys
Incisive
Cadence
Questa
Mentor
Design Flow
Design Details
Assertion Based
Verification
Tools
Company
SVA
OVL
CBV
FrontEnd-BackEnd
CDC
0-In CDC
Mentor
ECO
nECO
SpringSoft/Novas
Low Power Analysis
Power Compiler
Synopsys
Power Theater
Sequence
Emulation
Palladium
Cadence
Synthesis
Design Compiler
Synopsys
RTL Compiler
Cadence
Physical Compiler
Synopsys
PrimeTime
Synopsys
DFT Compiler
Synopsys
BSD Compiler
Synopsys
DFT MAX
Synopsys
TetraMAX ATPG
Synopsys
Encounter
Cadence
Silicon Ensemble
Cadence
IC Compiler
Synopsys
STA
DFT
Appollo
LVS/DRC
Magma
Magma
Dracula
Cadence
Hercules
Synopsys
Calibre
Mentor Graphics