FPGA DEVELOPMENT BOARD
USERS MANUAL
Initial Draft
Model RN-FDB
For assistance please contact REINFOLD
[email protected]www.reinfold.net
Ph: +91-80-36833572
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1
1.1
RN-FDB01 FPGA DEVELOPMENT BOARD
Introduction
1.2
Installation
1.2.1
Installing Xilinx Webpack
1.2.2
Applying Power To RN-FDB Board
1.2.3
Connecting a PC To RN-FDB Board
1.2.4
Connecting a VGA monitor to RN-FDB Board
1.2.5
Connecting a Mouse or Keyboard to RN-FDB Board
4
4
4
4
4
4
1.3
Programming
1.3.1
Downloading Non-Volatile Bitstreams INTO FPGA using xilinx impact.
5
5
1.4
Programmers Models
1.4.1
RN-FDB board organization and Functional description
5
5
1.5
Functional Description
1.5.1
Programmable Logic:
1.5.2
Interfacing Modules
1.5.3
Serial Programming
1.5.4
VGA Port
1.5.5
PS2 Port
1.5.6
General Purpose Input and Output
1.5.7
Seven-Segment LED[FND]
1.5.8
Oscillator
6
6
7
9
9
10
10
11
11
1.6
12
PIN ASSIGNMENT
1.7
SCHEMATICS
1.7.1
General purpose I/O and FND
1.7.2
Interfacing Modules
1.7.3
Power Circuitry
1.7.4
FPGA AND PROM CONNECTIONS
14
14
17
19
20
1.8
APPENDIX:
1.8.1
External Interfacing Modules
21
21
Figure 1-1: Arrangement Of Components On Board
Figure 1-2 : Stepper motor Bipolar Drive
Figure 1-3: 5X4 Keypad
Figure 1-4: Serial Port connection Dig
Figure 1-5: VGA Port Connection Dig
Figure 1-6: PS2 Port Connection Dig
Figure 1-7:D Flip Flop and Clock Pulse.
Figure 1-8: FND Arrangement Diagram
6
8
8
9
9
10
11
11
Table 1-1 :Switching Sequence
Table 1-2: FPGA Pin Assignment
Table 1-3:FPGA pin assignment for input and output leds
Table 1-4: Pin connections for external interfacing modules
8
12
13
21
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1 RN-FDB01 FPGA Development Board
1.1 Introduction
Designers may use the new XC3S50-5PQ208 in-system-programming (ISP) demo board to prototype, debug,
and troubleshoot small designs.The Demo Board has all the required Interfacing Modules On board which makes
the user easy to use and to debug.The additional Feature of RN-FDB board is it has a provision to use additional
interfacing circuit from the outside world. When used with the new Foundation Series or Alliance Series or
WebPack software, the board demonstrates the benefits of combining a robust pin-locking architecture with ISP.
The RN-FDB01 FPGA Demo-board provides an ideal platform for new engineers requiring experience with basic
digital design techniques, as well as those needing exposure to Xilinx CAD tools and FPGA devices.
The RN-CB01 FPGA Demo-board features include:
A socketed Xilinx XC3S50-5PQ208 FPGA device containing 5,292 logic cells with 50,000 system
gates(logic & RAM).
Non-volatility i.e., designs remain in the FPGA even after power is switched off.This feature is due to the
presence of external PROM on board. Configuration data can be read from an external serial PROM
(master serial mode), or written into the FPGA in slave serial, slave parallel, or boundary scan mode.
On board JTAG circuitry, that connects directly with PC through parallel port cable.
External JTAG cable connection facility.
16 input and output LEDs controlled by DIP switch.
Three PushButton switches that generate positive and negative pulsesand also manual clock.
Four highly-bright seven segment displays.
Provision of on board interfacing modules like DAC,ADC,Stepper,Relay,Keypad, and LCD.
Additional Feature of serial programming with Serial port,VGA Port and PS2 Port for Keypad or mouse
related designs.
10MHz on board, low jitter, high precision crystal oscillator.
Four 40-pin expansion connector used to connect off board interfacing circuits.
Unlimited reprogramming cycles are possible with this approach
Program/erase over full commercial voltage and temperature range.
The RN-FDB01 board makes excellent platform for instructional-lab based work. FPGAs are customized by
loading configuration data into internal static memory cells. Spartan-III FPGAs are typically used in high-volume
applications where the versatility of a fast programmable solution adds benefits.It is fully compatible with all
versions of Xilinx CAD tools, including free WebPack tools available at the Xilinx website. The included PGA uses
non-volatile configuration memory, so the design remains intact even on power off. The board is shipped with a
downloading cable, so designs can be implemented immediately without the need for any additional hardware.
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1.2 Installation
1.2.1 Installing Xilinx Webpack
XILINX currently provides the WebPACK tools for programming their CPLDs and Spartan series
FPGAs. You can also download the most current version of the WebPACK tools from the XILINX website.
1.2.1.1 Getting Help
Here are some places to get help if you encounter problems:
If you can't get the RN-FDB Board hardware to work, send an e-mail message describing your problem to
[email protected] or call on 080-51261526.
If you can't get your XILINX WebPACK software tools installed properly, send an email message
describing your problem to [email protected] or check their web site at
http://www.xilinx.com/support/support.htm
1.2.2 Applying Power To RN-FDB Board
RN-FDB Board has on board power supply with three regulators delivering 2.5V,3.3V and 5V power supply.To
power up the RN-FDB Board you can plug on the adaptor socket to the female jack available on the board. The
circuit on the board is powered by a 5 volt precisely regulated output of a bridge rectifier. This gives the user the
flexibility to use either AC or DC power supplies in the range of 6V to 9V with current limit of 500mA.
1.2.3 Connecting a PC To RN-FDB Board
The RN-FDB01 board uses a DB-25 parallel port connector to route JTAG programming signals from a host
computer to the RN-FDB board. A separate JTAG header is also provided so that a dedicated programming cable
(like the Xilinx Parallel III cable) can also be used. The programming circuit simply connects the parallel port pins
driven by the Xilinx CAD tools directly to the FPGA programming pins. The RN-FDB Demo-Board is therefore
compatible with all Xilinx programming tools.
nnecting
1.2.4 Connecting a VGA monitor to RN-FDB Board
You can display images on a VGA monitor by connecting it to the VGA port at the top of your RN-FDB Board (see
Figure 1-1 1). You will have to create a VGA display circuit for your RN-FDB Board to actually display an image.
1.2.5 Connecting a Mouse or Keyboard to RN-FDB Board
You can accept inputs from a keyboard or mouse by connecting it to the PS/2 port at the top of your RN-FDB
Board (see Figure 1-1). You will have to create a keyboard or mouse interface circuit to actually receive
information on keystrokes or mouse movements.
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1.3 Programming
1.3.1 Downloading Non-Volatile Bitstreams into FPGA using xilinx impact.
The RN-FDB Board consists of Two programming Devices PROM and FPGA.You can use the Xilinx iMPACT
software to download bitstreams to the RN-FDB Board.The iMPACT programming tool downloads bitstreams
through the JTAG interface of the FPGA.Follow the instructions for iMPACT to download bitstreams to the PROM
and FPGA.
Note that the PROM has to be programmed first to store the Non-Volatile Bitstreams.The presence of PROM
makes the device only needs to be reprogrammed once to support iMPACT because it retains its configuration
even when power is removed from the board.The program is retained in the PROM and so it retains the
configuration in the Flash memory even if the power is removed from the board.
1.4 Programmers Models
This section describes the various sections of the RN-FDB Board and shows how the I/O of the FPGA are
connected to the rest of the circuitry.. For more information, you can find a table of FPGA pin connections and
detailed schematics at the end of this manual.
1.4.1 RN-FDB board organization and Functional description
The RN-FDB01 board has been designed to offer a low cost and minimal system for designers who need a
flexible platform to gain exposure to the basics of hardware design and/or to FPGA devices. The RN-FDB board
provides sufficient I/Os and onboard interfacing modules that can be implemented without the need for any other
external devices.Figure 1-1 shows the Block diagram and the arrangement of Components on the RNFDB Board.
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ECO_JP3
RESET_B
9
16
INPUT LEDS
MCLK
FNDS
VGA PORT
OUTPUT LEDS
16
DIP SWITCH
12345678
DAC
STEPPER
CON7
RESET
D0
D1
D2
D3
D4
S0
S1
S2
S3
RELAY
TEMP_SENSOR
PUSHBOTTON
SWITCHES
40 PIN CONNECTOR
KEYPAD[5X4]
XC2 0 0 S-5 PQ 2 0 8
40 PIN CONNECTOR
FPGA
ECO_JP4
ECO_JP3
CLOCK
CON
ECO_JP5
40 PIN CONNECTOR
PARALLEL PORT
FRM
PC
OSC
SERIAL PORT
40 PIN CONNECTOR
JTAG
CON
10MHZ
PS2 PORT
lcd module(16X2)
PWR CON
PWR JACK
IC0832
ADC
BNC
12345678
IC0804
BNC
FF
Note: Usage of ECO_JP3,ECO_JP4,ECO_JP5,ECO_JP6 headers see APPENDIX
Figure 1-1: Arrangement Of Components On Board
1.5 Functional Description
1.5.1 Programmable Logic:
1.5.1.1 FPGA
The RNFDB Board contains two programmable logic chips:FPGA and PROM
FPGA is the main repository of programmable logic on the RN-FDB Board.A 50-Kgate XILINX Spartan-III FPGA
in a 208pin PQ package (XC3S50-5PQ208) is the main repository of programmable logic on the RN-FDB Board.
1.5.1.2 PROM
A 2Mbit Flash device provides non-volatile storage for data and FPGA configuration bit streams which is 20 pin
package.A Xilinx XCF02S PROM is used to manage the configuration of the FPGA via the parallel port. InSystem Programmable PROMs for Configuration of Xilinx FPGAs.Low-Power Advanced CMOS FLASH Process
has Endurance of 20,000 Program/Erase Cycles Operation over Full Boundary-Scan (JTAG) Support for
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Programming, Prototyping, and Testing JTAG Command .The I/O Pins on PROM are Compatible with Voltage
Levels Ranging From 1.5V to 3.3V.Design Support Using the Xilinx Alliance ISE and Foundation ISE Series
Software Packages XCF01S/XCF02S/XCF04S - 3.3V supply voltage are used for Serial FPGA configuration
interface.
1.5.2 Interfacing Modules
The following are the description of the on board interfacing modules.
NOTE: For pin assignment for all the following modules see Table 1-1 and Table 1-2.
1.5.2.1
Digital-To-Analog Convertor(DAC)
Short for Digital-to-Analog Converter, DAC is a device that reconstructs analog voltage waveforms from an
incoming sequence of binary digits.The DAC0832LCN used on RN-FDB Board is an advanced CMOS/Si-Cr 8-bit
multiplying DAC designed to interface directly with the 8080, 8048 and other popular microprocessors. The circuit
uses CMOS current switches and control logic to achieve low power consumption and low output leakage current
errors.Special circuitry provides TTL logic input voltage level compatibility.The Output Of the DAC is an analog
signal which can be viewed on a CRO.For Details u can find in the data sheet .
1.5.2.2 Analog-To-Digital Converter(ADC)
Analog-to-Digital Convertors are among the most widely used devices for data acquisition.We need ADC to
translate the analog signals to digital numbers .The ADC used on RNFDB Board is ADC0804.The ADC0804 IC is
an anlog-to-digital convertor in the family of ADC800 series from National Semiconductor.It works with +5V and
has the resolution of 8 bits.The ADC shown in Figure 1-1 has two BNC (red is for supply and Black is for
Ground).The Analog signals are applied to the two BNCs and the desired output ie the translated signals can be
viewed on the desired Display (Eg:FNDs,LCDs etc)
For further details and pin Diagram of the IC Refer Datasheet.
1.5.2.3 LM35-Temperature sensor:
Using ADC, temperature can be sensed easily and the values are displayed on FNDs.
1.5.2.4 Stepper Motor Drive
A stepper motor is widely used device that translates electricl pulses into mechanical movement.The stepper
motor is connected to the 7-pin connector shown in Figure 1-1: Arrangement Of Components On Board.
Below is the drive circuitry for Stepper motor which will be helpful for programming.
.
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Figure 1-2 : Stepper motor Bipolar Drive
Table 1-1 :Switching Sequence
A1
R
A3
O
B1
B
B3
G
The rotation direction is as viewed from the front end.
1.5.2.5 Relay
A relay, quite simply, is a small machine consisting of an electromagnet (coil), a switch, and a spring. The spring
holds the switch in one position, until a current is passed through the coil. The coil generates a magnetic field
which moves the switch. It's that simple. You can use a very small amount of current to activate a relay, and the
switch can often handle a lot.
Working of relay on RNFDB board is very simple. When the device is Programmed the relay operates with the
output visible on the Red led shown near the realy(in Figure 1-1).The led can be controlled via dipswitches.
1.5.2.6 Keypad
Keyboards and Keypads are another form of digital input. A keypad is a convenient way of entering data. The
keypad used on our board is 5X4 Matrix with 5 Drive lines as output and 4 Scan lines as inputs.A similar keypad
is as shown below.As per the designed circuit the keypad output can be viewed either on LCD or FNDs.
:
S0
S1
S2
S4
Figure 1-3: 5X4 Keypad
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1.5.2.7 LCD
LCD Another common type of seven segment display is Liquid crystal display.LCD operates by polarizing light so
that a nonactivated segment reflects incident light and thus appears invisible against its background. An activated
segment does not reflect incident light and thus appears dark.LCDs consume much less power than LEDs but
cannot be seen in dark ,while LEDs can.LCDs operate at low-frequency(30Hz-60Hz).
The LCD used is of 16X2LCD.
In LCD one can put data at any location.
For further details see 16X2 LCD Datasheet.
For LCD Datasheet Refer The 8051 Microcontroller and Embedded Systems by Mazidi.
1.5.3 Serial Programming
1.5.3.1 Serial Port
The term "serial port" is usually meant to identify hardware intended to interface with a modem or similar
communication devices. The concept behind serial communications is as follows, data is transferred from sender
to receiver one bit at a time through a single line or circuit. The serial port takes 8, 16 or 32 parallel bits from your
computer bus and converts it as an 8, 16 or 32 bit serial stream. The name serial communications comes from
this fact; each bit of information is transferred in series from one locations to another.
SERIAL PORT_DB9
164
TOUT
FPGA
MAX32
RIN
163
Figure 1-4: Serial Port connection Dig
.
1.5.4
VGA Port
The FPGA can generate a video signal for display on a VGA monitor. The RN-FDB Board can send signals to
display graphics on a VGA monitor through this port. The FPGA outputs three bits each of red, green, and blue
color information.This provides a palette of 2 x 2x 2 = 8 colors. The outputs sent to the RGB inputs of a VGA
monitor. The FPGA also generates the horizontal and vertical sync pulses (HSYNC#, VSYNC#).
Figure 1-5: VGA Port Connection Dig
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1.5.5
PS2 Port
A PS/2 port provides the FPGA with an interface to either a keyboard or a mouse. The
FPGA receives two signals from the each PS/2 interface: a clock signal and a serial data stream
that is synchronized with the falling edge of the clock.RN-FDB board has provided two PS/2 Port to make the end
user capable of using keyboard and mouse related designs simultaneously or as per users requirement.The
Figure 1-6 shows a PS/2 connections to the FPGA.
Figure 1-6: PS2 Port Connection Dig
1.5.6 General Purpose Input and Output
1.5.6.1 Dipswitches and LEDS
Two DIP switches are attached to the FPGA. A two DIP switch passes settings to the RN-FDB Board and controls
the input and output LEDs. When closed (ON), each switch pulls the
connected pin of the FPGA to ground. The pin is pulled high through a resistor when the
switch is open (OFF). Small resistors are placed in series between the FPGA and the switches so prevent
damage if the FPGA tries to drive a pin that is being pulled low.
A LED allows visible feedback as the RN-FDB Board operates.For the circuit u can see the schematics of general
purpose input and output
1.5.6.2 Pushbutton Switch
The FPGA also connects to three pushbuttons. Three pushbuttons send momentary contact information to the
FPGA. Each pushbutton applies a low level to its FPGA pin when pressed and a resistor pulls the pin to a high
level when the pushbutton is released.Each of the pushbottons are dedicated to Negative
Reset(Reset_b),Positive Reset(Reset) and manual Clock(Mclk) as shown in Figure 1-1.Small resistors are placed
in series between the FPGA and the pushbuttons to prevent damage if the FPGA tries to drive a pin that is being
pulled low.
Manual Clock(Mclk):This pushbutton is used as a manual clock.The user may give the clock manually
through the pushbutton. The clock is a sequence of high and low pulses,therefore when the pushbutton is
pressed, a low is applied and high when released.This Pushbutton sends contact information to FPGA
pin(P77) and the result is observed as designed.
For eg if u want a Dflip flop to be designed and provide a clock manually this can be done as follows.
The DFlip Flop has only one input. This input is called D or Data input.
D Flip Flop
D
CLK
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Manual Clock Pulse
Q
Qb
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Figure 1-7:D Flip Flop and Clock Pulse.
Always at the positive edge of clock, the output Q is assigned with the value of D (input value).And Qb the bar of
Q.So this Positive edge of clock(ie High Pulse) is given manually via Mclk Pushbutton when released and vice
versa.
1.5.7 Seven-Segment LED[FND]
The RN-FDB Board has a 4 FNDs.Segments of the LED glow when a logic-high level is applied to them.The
outputs can be displayed on each of the FNDs.The pin mapping of each FND is given in Table 1-2: FPGA P.
FND0
FND1
FND2
FND3
A
F
A
B
G
E
G
C
A
B
G
C
A
B
G
C
C
D
Figure 1-8: FND Arrangement Diagram
1.5.8 Oscillator
The RN-CB01 board provides user to use any one of the oscillators that are available on board. The oscillator
consists of low jitter high precession crystal oscillator of 10Mhz.
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1.6 PIN ASSIGNMENT
Table 1-2: FPGA Pin Assignment
FPGA
PIN NO
MAPPED TO
FPGA PIN NO.
DAC
P119
P120
P122
P123
P124
P125
P130
P131
P132
DAC[7]
DAC[6]
DAC[5]
DAC[4]
DAC[3]
DAC[2]
DAC[1]
DAC[0]
DAC_WR_B
ADC
P133
ADC_CHSEL[0]
P138
ADC_READ
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MAPPED TO
FPGA PIN NO.
LCD
KEYPAD
P175
P172
P171
P169
P168
P200
P154
P137
P167
LCD_DATA[7]
LCD_DATA[6]
LCD_DATA[5]
LCD_DATA[4]
LCD_DATA[3]
LCD_DATA[2]
LCD_DATA[1]
LCD_DATA[0]
LCD_ E
P166
LCD_RNW
P165
LCD_RS
RELAY
12
MAPPED TO
P198
P197
P196
P194
P191
P190
P189
P187
P185
DRV4
DRV3
DRV2
DRV1
DRV0
SCAN3
SCAN2
SCAN1
SCAN0
PS2 PORT
P205
PS2_1_DATA
P181
PS2_1_CLK
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P139
ADC_WRITE
P152
P150
ADC_INTR
P140
P141
P143
P144
ADC[7]
ADC[6]
ADC[5]
ADC[4]
P155
P156
P161
P162
P146
P147
P148
ADC[3]
ADC[2]
ADC[1]
P182
P178
P149
ADC[0]
RELAY_ON_OUT
STEPPER MOTOR
STPR_R
STPR_O
STPR_B
STPR_G
SERIAL PORT
FPGA_RIN
FPGA_TOUT
P204
PS2_0_DATA
P180
PS2_0_CLK
VGA PORT
P176
P52
FPGA_VSYNC
FPGA_HSYNC
P51
P48
P46
RED
GREEN
BLUE
SEVEN SEGMENT DISPLAY
FND0
FND2
P2
P3
P7
F0A
F0B
F0C
P26
P27
P28
F2A
F2B
F2C
PUSHBUTTON SWITCHES
SW1 (neg pulse)
P79
SW2 (pos pulse)
P80
SW3[ (Mclk)]
P76
P9
P10
F0D
F0E
P29
P34
F2D
F2E
CLOCK (Internal 4Mhz or 10Mhz)
P77
CLK
P11
P12
P4
F0F
F0G
F0H
P35
P36
P22
F2F
F2G
F2H
F1A
F1B
F1C
F1D
F1E
F1F
F1G
F1H
P37
P39
P40
P42
P43
P44
P45
P24
FND1
P13
P15
P16
P18
P19
P20
P21
P5
FND3
F3A
F3B
F3C
F3D
F3E
F3F
F3G
F3H
Note:F0A:F0=FND0 and A is segment A of FND0.Details see Figure 1-8 for FND Dig.,
Table 1-3:FPGA pin assignment for input and output leds
GENERAL PURPOSE INPUT[DIPSWITCHES] AND OUTPUTS[LEDS]
P57
P58
P61
P62
P63
P64
P65
P67
DIPSWITCHES[INPUT]
SW0
SW 1
SW 2
SW 3
SW 4
SW 5
SW 6
SW 7
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LEDS[OUTPUT]
P87
P90
P93
P94
P95
P100
P101
P102
13
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
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P68
P71
P72
P74
P78
P81
P85
P86
SW 8
SW 9
SW10
SW11
SW12
SW13
SW14
SW15
P106
P107
P111
P113
P114
P115
P116
P117
LED8
LED9
LED10
LED11
LED12
LED13
LED14
LED15
1.7 SCHEMATICS
1.7.1 General purpose I/O and FND
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GENERAL PURPOSE PERIPHERALS
OUTPUT_LEDS
D5
D7
LED9
D9
LED10
D11
LED11
D13
LED12
D15
LED13
D17
LED14
D19
LED15
D6
LED0
LED
D8
LED1
LED
D10
LED2
LED
D12
LED3
LED
D14
LED4
LED
D16
LED5
LED
D18
LED6
LED
D20
LED7
LED
LED
LED
LED
LED
LED
9
8
7
6
5
4
3
2
LED
9
8
7
6
5
4
3
2
9
8
7
6
5
4
3
2
LED
LED
9
8
7
6
5
4
3
2
OUTPUT_LEDS
LED8
R34
R-PACK
R33
R-PACK
R32
R-PACK
R31
R-PACK
GPIO_3.3V_POS
SW5
D37
R41
LED
LED
D27
LED
D30
LED
D28
LED
D29
LED
9
8
7
6
5
4
3
2
LED
SW DIP-8
R-PACK
R43
50E
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DSI0
DSI1
DSI2
DSI3
DSI4
DSI5
DSI6
DSI7
D26
LED
LED
D24
LED
D34
LED
D25
LED
D36
LED
D23
LED
D31
LED
R39
R-PACK
D32
9
8
7
6
5
4
3
2
SW DIP-8
INPUT_SWITCHES
LED
DSI8
DSI9
DSI10
DSI11
DSI12
DSI13
DSI14
DSI15
16
15
14
13
12
11
10
9
D33
INPUT_SWITCHES
1
2
3
4
5
6
7
8
D38
16
15
14
13
12
11
10
9
D35
SW4
1
2
3
4
5
6
7
8
R44
50E
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g
f
GND
a
b
U19
10
9
8
7
6
F3A
F3B
F3C
F3D
F3E
F3F
F3G
F3H
1
2
3
4
5
e
d
GND
c
dp
FND3
R57
R
JP3
D3.3V_POS
F0A
F0B
F0C
F0D
F0E
F0F
F0G
F0H
F1A
F1B
F1C
F1D
F1E
F1F
F1G
F1H
D2.5V_POS
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
39
JP6
2
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
40
D3.3V_POS
F2A
F2B
F2C
F2D
F2E
F2F
F2G
F2H
F3A
F3B
F3C
F3D
F3E
F3F
F3G
F3H
DSI0
DSI1
DSI2
DSI3
DSI4
DSI5
DSI6
DSI7
DSI8
DSI9
DSI10
DSI11
DSI12
DSI13
DSI14
DSI15
MCLK0
CLK0
D2.5V_POS
Header_ch
Confidential
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
39
2
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
40
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
LED9
LED10
LED11
LED12
LED13
LED14
LED15
RESET0_B
RESET0
Header_ch
16
Sunday, September 07, 2003
1.7.2 Interfacing Modules
DAC AND ADC MODULES
U6
ALLIF_5V_POS
2
U15
CS_b
RD_b
WR_b
INTRb
1K
DAC0_WR_B
6
5
R46
3K
7
LM358
U8B
R45
200E
18
17
16
15
14
13
12
11
ADC_IN[0]
ADC_IN[1]
J7
ADC_IN[2]
1
ADC_IN[3]
ADC_IN[4]
CON1ADC_IN[5]
ADC_IN[6]
ADC_IN[7]
J8
1
DAC0832
VCC
CLK_R
CLK_in
20
19
18
2
1
9
11
12
10
3
3
2
DI0
Vcc
DI1
ILE
DI2 WR2b
DI3 WR1b
DI4 CSbar
DI5
Rf b
DI6
Iout1
DI7
Iout2
XFERbGND
Vref
GND
1K
ECO_R40
7
6
5
4
16
15
14
13
17
8
DAC_IN[0]
DAC_IN[1]
DAC_IN[2]
DAC_IN[3]
DAC_IN[4]
DAC_IN[5]
DAC_IN[6]
DAC_IN[7]
ALLIF_5V_POS
R40
1
2
3
5
ADC_CHSEL[0]
ADC_READ
ADC_WRITE
ADC_INTR
D0
D1
D2
D3
D4
D5
D6
D7
+Vin
20
19
ALLIF_5V_POS
ECO_C9
ECO_R25
10K
150pF
ADC_PVIN
J5
-Vin
Vref /2
A_GND
D_GND
8
10
CON1
CON1
ADC0804
ALLIF_5V_POS
TEMPERATURE SENSOR
TEMP_SENSOR_OUT
J4
R26
3K
VOUT +VS
TEMP_SENSOR
GND
TEMP_SENSOR_OUT
1K
R30
CON1
ECO_KK8
LM358
3
STEPPER MOTOR
U10
STPR_R
STPR_O
STPR_B
STPR_G
1
2
3
4
5
6
7
8
1B
1C
2B
2C
3B
3C
4B
4C
5B
5C
6B
6C
7B
7C
E
COM
16
15
14
13
12
11
10
9
STPROUT_Y
STPROUT_O
STPROUT_BL
STPROUT_BR
ALLIF_5V_pos
STPROUT_Y
STPROUT_O
STPROUT_BL
STPROUT_BR
ALLIF_5V_pos
ULN2003A
JP4
D3.3V_POS
IO102
DAC_IN[7]
DAC_IN[6]
DAC_IN[5]
DAC_IN[4]
DAC_IN[3]
DAC_IN[2]
DAC_IN[1]
DAC_IN[0]
DAC0_WR_b
IO135
IO142
IO146
D2.5V_POS
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
39
2
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
40
ADC_CHSEL[0]
ADC_READ
ADC_WRITE
ADC_IN[7]
ADC_IN[6]
ADC_IN[5]
ADC_IN[4]
ADC_IN[3]
ADC_IN[2]
ADC_IN[1]
ADC_IN[0]
ADC_INTR
RELAY _CTRL_B
STPR_R
STPR_O
STPR_B
STPR_G
Header_ch
Confidential
ADC_PVIN
JUMPER
U8A
1
R25
200E
JUMPER ECO_JP1
1
2
ECO_JP2
1
2
17
Sunday, September 07, 2003
ECO_J6
1
2
3
4
5
6
7
CON7
ALLIF_5V_POS
LCD_INTERFACE_16x2
U12
U13
VCC
CON
RS
RW
E
D0
D1
D2
D3
D4
D5
D6
D7
LED_A
LED_K
ALLIF_5V_pos
1
2
3
F_LCD1
POT
F_LCD2
LCD_RS
LCD_RW
F_LCD0
F_LCD0
R42
F_LCD3
GND
F_LCD1
F_LCD2
F_LCD3
1A1
Vcc
1A2
1A3
1Y 1
1A4
1Y 2
1Y 3
LCD_E
LCD_DATA0
LCD_DATA1
8
9
LCD_DATA2
10
LCD_DATA3
11
LCD_DATA4
12
LCD_DATA5
13
LCD_DATA6
14
LCD_DATA7
F_LCD4
LCD_DATA0
F_LCD5
LCD_DATA1
F_LCD6
LCD_DATA2
F_LCD7
11
F_LCD5
13
F_LCD6
15
F_LCD7
17
2A1
1Y 4
2A2
2Y 1
2A3
2Y 2
2A4
LCD_DATA3
2Y 3
LCD_DATA4
R4947E
D5V_POS
19
LCD_DATA5
LCD_DATA6
LCD_DATA7
2Y 4
18
LCD_DATA0
16
LCD_DATA1
14
LCD_DATA2
12
LCD_DATA3
LCD_DATA4
LCD_DATA5
LCD_DATA6
LCD_DATA7
LCD_DATA0
LCD_DATA1
LCD_DATA2
LCD_DATA3
LCD_DATA4
LCD_DATA5
LCD_DATA6
LCD_DATA7
2G
1G_b
GND
10
R50
ALLIF_5V_POS
74LS241
50E
R52100E
15
16
F_LCD4
20
R53
1K
LCD16x2
CONNECTORS
ALLIF_5V_POS
0.1uF C10
U9
1
C11
0.1uF
2
3
4
C12
0.1uF
5
6
0.1uF
C13
7
8
P1
C1+
VCC
V+
GND
C1-
T1OUT
C2+
R1IN
C2-
R1OUT
V-
T1IN
T2OUT
T2IN
16
15
14
FPGA_VSYNC
13
FPGA_HSYNC
12
FPGA_RIN
11
FPGA_TOUT
10
09
R2IN R2OUT
MAX232
P2
5
9
4
8
3
7
2
6
1
1
BLUE
GREEN
RED
R 2
R
3
R
8
15
7
14
6
13
5
12
4
11
3
10
2
9
1
U20
1
DRV0
DRV1
DRV2
DRV3
DRV4
SCAN0
SCAN1
SCAN2
SCAN3
DRV0
DRV1
DRV2
DRV3
DRV4
SCAN0
SCAN1
SCAN2
SCAN3
R23
10k
R24
10k
JS1
1
2
3
6
5
4
M-DIN_6-R
VGACONNECTOR
RS232_9pinCON
KEYPAD5x4 MATRIX SECTION
KEYBOARD MOUSE PS2
CONNECTORS
ALLIF_5V_POS
JP5
D3.3V_POS
F_LCD_RS
F_LCD_RW
F_LCD_E
F_LCD0
F_LCD1
F_LCD2
F_LCD3
F_LCD4
F_LCD5
F_LCD6
F_LCD7
SCAN0
SCAN1
SCAN2
SCAN3
DRV0
DRV1
DRV2
D2.5V_POS
KEY PAD_PORT5x4
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
39
2
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
40
DRV3
DRV4
PS2_0_CLK
PS2_0_DATA
PS2_1_CLK
PS2_1_DATA
BLUE
GREEN
RED
FPGA_HSY NC
FPGA_VSY NC
FPGA_TOUT
FPGA_RIN
TCK
TMS
FPGA_TDI
TDO
IO162
Header_ch
5
4
3
2
1
R58
Confidential
18
Sunday, September 07, 2003
PS2_0_CLK
PS2_0_DATA
1.7.3 Power Circuitry
U21
J9
PLUG AC FEMALE
3
IN
BRIDGE
D41
+ 3
R59
100
R60
R
R61
4 -
OUT
ADJ
D5V_POS
STLM317
C16
3500UF
C17
2200UF
D42
C15
1UF
R62
370
C18
10UF/25V
LED
U22
3
OUT
ADJ
IN
D3.3V_POS
STLM317
R63
100
R64
R
C21
10UF/25V
R65
220
C20
1UF
U23
IN
OUT
2
R66
200
R67
R
1
C24
10UF/25V
R68
220
C23
1UF
POWER BUS CHAINING CONNECTOR
CON4
4
3
2
1
J10
CON4
4
3
2
1
J11
DGND
F1
FUSE
F2
FUSE
F3
FUSE
DGND
GROUND CHAINING CONNECTOR
J12
D2.5V_POS
D3.3V_POS
D5V_POS
Confidential
CON1
19
LED
D2.5V_POS
STLM317
ADJ
D45
Sunday, September 07, 2003
D48
RED LED
1.7.4 FPGA AND PROM CONNECTIONS
D3.3V_pos
D2.5V_pos
C1
C
C2
C
C3
C
C4
C
C5
C
C6
C
C7
C
C8
C
C9
C
C10
C
C11
C
C12
C
C13
C
C14
C
C15
C
C16
C
D2.5V_pos
D3.3V_pos
D3.3V_pos
U1
PROM-CIRCUITRY
56
55
198
190
183
177
169
158
145
137
131
124
116
103
93
85
79
72
64
51
40
32
25
19
11
1
196
186
171
143
128
118
91
76
66
38
28
13
208
197
184
170
156
144
130
117
105
92
78
65
53
39
R1
R2
3.3K
26
12
155
207
2
159
157
104
185
182
77
80
161
160
107
106
154
108
126
135
142
146
153
54
50
52
132
129
27
24
206
205
204
203
202
201
200
199
195
194
193
192
191
189
188
187
181
180
179
178
176
175
R3
3.3K
PROM_CCLK
TCK
TMS
TDI
TDO
PROM_DONE
3
2
1
20
19
PROM_DIN
PROM_CCLK
U2
CLK
D2
D0
Vccint
Vcco
MCLK0
CLK0
PROM_INIT_b
PROM_PROGRAM_b
4
5
6
7
8
PROM_PROGRAM_b
PROM_INIT_b
TDI
TMS
XC18V512_PROM
TCK
VQ44-pinPackage
D4/CF_b
OE/RESET_b
Vccint
TDO
D1
D3
D5
18
17
16
15
14
PROM_TDO
D6
CE_b
GND
D7
CEO_b
IO135
IO142
IO146
PROM_DIN
9
10
11
12
13
VCCO
VCCO
CCLK
TCK
TMS
TDI
TDO
DONE
I, GCK3
I, GCK2
I, GCK1
I, GCK0
I/O (WRITE) BAR
I/O (CS) BAR
I/O (INIT) BAR
PROGRAM BAR
I/O (DOUT, BUSY)
I/O D(7)
I/O D(4)
I/O D(3)
I/O D(2)
I/O (D1)
I/O (DIN, D0)
M2
M1
M0
I/O IRDY(1)
I/O TRDY(1)
I/O TRDY(1)
I/O IRDY(1)
I/O
I/O VREF
I/O
I/O VREF
I/O
I/O
I/O VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O VREF
I/O
I/O
I/O
I/O
I/O
I/O VREF
I/O
I/O
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
(D6)
(D5)
VREF
VREF
VREF
VREF
VREF
XC2S200_PQ208
VREF
I/O
I/O VREF
I/O
I/O VREF
I/O
I/O
I/O VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O VREF
I/O
I/O
I/O
I/O
I/O
I/O VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O VREF
I/O
I/O
I/O VREF
I/O VREF
I/O
I/O
I/O
I/O VREF
I/O
I/O VREF
I/O
I/O
I/O VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O VREF
I/O
I/O
I/O
I/O
I/O
F_LCD_RS
F_LCD_RW
F_LCD_E
F_LCD0
F_LCD1
F_LCD2
F_LCD3
F_LCD4
F_LCD5
F_LCD6
F_LCD7
SCAN0
SCAN1
SCAN2
SCAN3
DRV0
DRV1
DRV2
DRV3
DRV4
PS2_0_CLK
PS2_0_DATA
PROM_DONE
TCK
TMS
FPGA_TDI
JP1
1
TDI
1
2
JUMPER
JP2
2
FPGA_TDI
PROM_TDO
JUMPER
U3
D3.3V_pos
F0a
F0b
F0c
F0d
F0e
F0f
F0g
F0h
F1a
F1b
F1c
F1d
F1e
F1f
F1g
F1h
D2.5V_pos
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
39
U6
2
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
40
Header_ch
F2a
F2b
F2c
F2d
F2e
F2f
F2g
F2h
F3a
F3b
F3c
F3d
F3e
F3f
F3g
F3h
D3.3V_pos
DSI0
DSI1
DSI2
DSI3
DSI4
DSI5
DSI6
DSI7
DSI8
DSI9
DSI10
DSI11
DSI12
DSI13
DSI14
DSI15
MCLK0
CLK0
D2.5V_pos
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
39
FPGA_RIN
FPGA_TOUT
FPGA_VSYNC
FPGA_HSYNC
RED
GREEN
BLUE
PS2_1_DATA
PS2_1_CLK
IO162
IO102
LED4
LED5
LED6
LED7
LED8
LED9
LED10
LED11
LED12
LED13
LED14
LED15
RESET0_b
RESET0
DAC_IN[7]
DAC_IN[6]
DAC_IN[5]
DAC_IN[4]
DAC_IN[3]
DAC_IN[2]
DAC_IN[1]
DAC_IN[0]
DAC0_WR_b
ADC_CHSEL[0]
ADC_READ
ADC_WRITE
ADC_IN[7]
ADC_IN[6]
ADC_IN[5]
ADC_IN[4]
ADC_IN[3]
ADC_IN[2]
ADC_IN[1]
ADC_IN[0]
ADC_INTR
FPGA_ADC_CLK
RELAY_CTRL_b
STPR_R
STPR_O
STPR_B
STPR_G
84
86
87
88
89
90
94
95
96
97
98
99
100
101
102
109
110
111
112
113
114
115
119
120
121
122
123
125
127
133
134
136
138
139
140
141
147
148
149
150
151
152
162
163
164
165
166
167
168
172
173
174
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
3
4
5
6
7
8
9
10
14
15
16
17
18
20
21
22
23
29
30
31
33
34
35
36
37
41
42
43
44
45
47
46
48
49
57
58
59
60
61
62
63
67
68
69
70
71
73
74
75
81
82
83
NC
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC INT
VCC INT
VCC INT
VCC INT
VCC INT
VCC INT
VCC INT
VCC INT
VCC INT
VCC INT
VCC INT
VCC INT
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
4.7K
F0a
F0b
F0c
F0d
F0e
F0f
F0g
F0h
F1a
F1b
F1c
F1d
F1e
F1f
F1g
F1h
F2a
F2b
F2c
F2d
F2e
F2f
F2g
F2h
F3a
F3b
F3c
F3d
F3e
F3f
F3g
F3h
DSI0
DSI1
DSI2
DSI3
DSI4
DSI5
DSI6
DSI7
DSI8
DSI9
DSI10
DSI11
DSI12
DSI13
DSI14
DSI15
LED0
LED1
LED2
LED3
U4
2
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
40
Header_ch
D3.3V_pos
LED0
PROM_DONE
LED1 PROM_PROGRAM_b
LED2
PROM_INIT_b
LED3
PROM_DIN
LED4
PROM_CCLK
LED5
IO102
LED6
DAC_IN[7]
LED7
DAC_IN[6]
LED8
DAC_IN[5]
LED9
DAC_IN[4]
LED10
DAC_IN[3]
LED11
DAC_IN[2]
LED12
DAC_IN[1]
LED13
DAC_IN[0]
LED14
DAC0_WR_b
LED15
IO135
RESET0_b
IO142
RESET0
IO146
D2.5V_pos
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
39
U5
2
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
40
ADC_CHSEL[0]
ADC_READ
ADC_WRITE
ADC_IN[7]
ADC_IN[6]
ADC_IN[5]
ADC_IN[4]
ADC_IN[3]
ADC_IN[2]
ADC_IN[1]
ADC_IN[0]
ADC_INTR
FPGA_ADC_CLK
RELAY_CTRL_b
STPR_R
STPR_O
STPR_B
STPR_G
Header_ch
D3.3V_pos
F_LCD_RS
F_LCD_RW
F_LCD_E
F_LCD0
F_LCD1
F_LCD2
F_LCD3
F_LCD4
F_LCD5
F_LCD6
F_LCD7
SCAN0
SCAN1
SCAN2
SCAN3
DRV0
DRV1
DRV2
D2.5V_pos
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
39
2
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
40
DRV3
DRV4
PS2_0_CLK
PS2_0_DATA
PS2_1_CLK
PS2_1_DATA
BLUE
GREEN
RED
FPGA_HSYNC
FPGA_VSYNC
FPGA_TOUT
FPGA_RIN
TCK
TMS
FPGA_TDI
TDO
IO162
Title
<Title>
Header_ch
Size
C
Date:
Confidential
20
Document Number
<Doc>
Saturday , December 10, 2005
Sunday, September 07, 2003
Rev
Sheet
of
1.8 APPENDIX:
1.8.1 External Interfacing Modules
The Board has 40pin extension connectors named ECO_JP3, ECO_JP4, ECO_JP5, ECO_JP6(see Figure 1-1 1)
which can be utilized for external interfacing modules.Each of the 40pin connectors are connected to FPGA The
user may use the additional connectors for connecting external circuits as per the requirement.The board has
additional two 4pin power connector(pwr con) for power chaining to external interfacing modules(see Figure
1-1).The 40 pin extension pin connections are given in Table 1-4.
Table 1-4: Pin connections for external interfacing modules
40 PIN EXTENSION CONNECTOR
EXT PIN No.
ECO_JP3
ECO_JP4
ECO_JP5
ECO_JP6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
NC
NC
F0A
F0B
F0C
F0D
F0E
F0F
F0G
F0H
F1A
F1B
F1C
F1D
F1E
F1F
F1G
F1H
F2A
F2B
F2C
F2D
F2E
F2F
F2G
F2H
F3A
F3B
F3C
F3D
F3E
F3F
F3G
NC
NC
NC
NC
NC
NC
NC
IO102
DAC[7]
DAC[6]
DAC[5]
DAC[4]
DAC[3]
DAC2]
DAC[1]
DAC[0]
DAC_WR_B
IO135
IO142
IO146
ADC_CHSEL
ADC_READ
ADC_WRITE
ADC[7]
ADC[6]
ADC[5]
ADC[4]
ADC[3]
ADC[2]
ADC[1]
ADC[0]
ADC_INTR
NC
NC
NC
LCD_RS
LCD_RW
LCD_E
LCD[0]
LCD[1]
LCD[2]
LCD[3]
LCD[4]
LCD[5]
LCD[6]
LCD[7]
SCAN[0]
SCAN[1]
SCAN[2]
SCAN[3]
DRV[0]
DRV[1]
DRV[2]
DRV[3]
DRV[4]
PS2_0_CLK
PS2_0_DATA
PS2_1_CLK
PS2_0_DATA
BLUE
GREEN
RED
FPGA_HSYNC
FPGA_VSYNC
FPGA_TOUT
FPGA_RIN
NC
NC
SW0
SW 1
SW 2
SW 3
SW 4
SW 5
SW 6
SW 7
SW 8
SW 9
SW10
SW11
SW12
SW13
SW14
SW15
MCLK0
CLK0
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
LED9
LED10
LED11
LED12
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34
35
36
37
38
39
40
F3H
NC
NC
NC
NC
NC
NC
RELAY_CTRL_B
STPR_R
STPR_O
STPR_B
STPR_G
NC
NC
TCK
TMS
FPGA_TDI
TDO
IO162
NC
NC
LED13
LED14
LED15
NC
NC
NC
NC
NC:NOT CONNECTED
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