5 Bit Flash ADC Pipeline Converter
Project, EE-288
Arunagiri Pattabi
San Jose State University
[email protected]
Abstract To design a 5 bit Flash ADC using the given 45nm
CMOS technology. The Flash ADC is the fastest ADC compared to
Pipeline or SAR adc.
I.
library. Following is the schematics and symbol of the 2 input
OR gate which is used in the ADC design
INVERTER LOGIC:
The Inverter is built using the 45nm Nmos and Pmos gates
which are available in the provided gpdk045 library.
Following is the schematics and symbol of the only Inverter
which is used in the ADC design
Fig. 1.
Fig. 3.
2-input OR gate schematic
Fig. 4.
2-input OR gate symbol
Inverter schematic
III.
Fig. 2.
Inverter symbol
II.
TWO INPUT OR GATE:
The Two input OR gate is built using the 45nm Nmos and
Pmos gates which are available in the provided gpdk045
THREE INPUT OR GATE:
The Three input OR gate is built using the 45nm Nmos and
Pmos gates which are available in the provided gpdk045
library. Following is the schematics and symbol of the 3 input
OR gate which is used in the ADC design
Fig. 5.
3-input OR gate schematic
Fig. 8.
4-input OR gate schematic
V.
TWO INPUT AND GATE:
The Two input AND gate is built using the 45nm Nmos and
Pmos gates which are available in the provided gpdk045
library. Following is the schematics and symbol of the 2 input
AND gate which is used in the ADC design
Fig. 6.
3-input OR gate schematic
IV.
FOUR INPUT OR GATE:
The Four input OR gate is built using the 45nm Nmos and
Pmos gates which are available in the provided gpdk045
library. Following is the schematics and symbol of the 4 input
OR gate which is used in the ADC design
Fig. 7.
4-input OR gate schematic
Fig. 9.
2-input AND gate schematic
Fig. 10.
2-input AND gate schematic
VI.
THREE INPUT AND GATE:
The Three input AND gate is built using the 45nm Nmos and
Pmos gates which are available in the provided gpdk045
library. Following is the schematics and symbol of the 3 input
AND gate which is used in the ADC design
Fig. 13.
input AND gate schematic
Fig. 14.
Fig. 11.
4-
4-input AND gate schematic
3-input AND gate schematic
VIII. THERMOMETER TO GRAY CODE CONVERTER:
This is one of the important stage in the ADC which converts
from 2^n-1 number of inputs to n outputs. The advantage of
this intermediate stage before converting the thermometer
code to binary is that, this code has only one bit changing from
the previous input to the current input when a linearly
changing input is applied. There are so many types of
Decoders available. I have used the following Decoder whose
schematics, symbol is given below.
Fig. 12.
3-input AND gate schematic
VII.
FOUR INPUT AND GATE:
The Four input AND gate is built using the 45nm Nmos and
Pmos gates which are available in the provided gpdk045
library. Following is the schematics and symbol of the 4 input
AND gate which is used in the ADC design
Fig. 15.
Thermometer to Gray code schematic
Fig. 16.
Fig. 17.
Gray to Binary code schematic
Fig. 18.
Gray to Binary code symbol
Thermometer to Gray code symbol
The Schematics of theThermometer to Gray code decoder is drawn on the
following logic. Note: For readers easiness, I have shortened the signal name
Gray_code[4:0] to G[4:0] and Thermometer_code[31:1] to T[31:1]
G[4] = (T[17] | T[16]) & T[15] & T[14]
G[3] = T[8] & T[7] & !T[24] & !T[25]
G[2] = (T[4] & T[3] & !T[12] & !T[13]) | (T[20] & T[19] & !
T[28] & !T[29])
G[1] = (T[2] & T[1] & !T[6] & !T[7]) | (T[10] & T[9] & !T[14]
& !T[15]) | (T[18] & T[17] & !T[22] & !T[23]) | (T[26] & T[25]
& !T[30] & !T[31])
G[1] = ( {T[1] | T[2]} & !T[3] & !T[4]) | ({T5] | T[6]} & !T[7]
& !T[8]) | ({T[9] | T[10]} & !T[11] & !T[12]) | ({T[13] | T[14]} & !
T[15] & !T[16]) | ({T[17] | T[18]} & !T[19] & !T[20]) | ({T[21] |
T[22]} & !T[23] & !T[24]) | ({T[25] | T[26]} & !T[27] & !T[28]) |
({T[29] | T[30]} & !T[31])
The Logic of the Gray to Binary Conversion is a mere
implementation of the following verilog equivalent code.
Though the Gray_code[4] is as simple as T[16]. To avoid any bubble error
propogating beyond this point, We add additional conditions like Ored with
T[17] and the lowered bits like (T15, T14 etc) has to be one. Its always
recommened to use strict conditions at the MSB, since an error in this bit
means the ADC is unreliable as it works falsely for more than 50% error of
the total input. Similarly, the main logic condition for,
G[3] = T[3] & !T[24],
G[2] = (T[4] &!T[12]) | (T[20] & !T[28]),
G[1] = (T[2] & !T[6]) | (T[10] & !T[14]) | (T[18] & !T[22]) | (T[26] & !T[30])
G[0] = (T[1] & !T[3]) | (T[5] & !T[7]) | (T[9] & !T[11]) | (T[13] & !T[15])
| (T[17] & !T[19]) | (T[21] & !T[23]) | (T[25] & !T[27]) | (T[29] & !T[31])
Hence, the extra conditions are added in the logic generation of
Gray code to prevent the Bubble error propogation.
IX.
GRAY CODE TO BINERY CODE CONVERTER:
This is the final stage in the ADC which converts the gray
code into the Human readable/recognizable binary format
code. It is at this stage we will get the final Digital Equivalent
of the Analog input we apply at the input.
//Verilog HDL for "ee288", "gray2bin_5" "Verilog"
module gray2bin (clk, gray_code[4:0], bin_code[4:0], vddc, gnd);
input wire clk;
input wire [4:0] gray_code;
output reg [4:0] bin_code;
input wire vddc;
input wire gnd;
reg [4:0] gray_code_stored;
always @ (posedge clk) begin
gray_code_stored <= gray_code;
bin_code <= gray2bin(gray_code_stored);
end
function [4:0] gray2bin;
input [4:0] ptr;
integer i, j;
begin
for (i = 0; i < 5 ; i = i + 1) begin
gray2bin[i] = ptr[i];
for (j = 1; j < 5 ; j = j + 1) begin
if (j > i)
gray2bin[i] = gray2bin[i] ^ ptr[j];
end
end
end
endfunction
endmodule
X.
TRACK AND HOLD CIRCUIT:
This is the initial stage in the ADC which stores the voltage
value of the input signal and passes it to the comparator in the
next stage. This is made of pmos and nmos pair, which works
for all variations in the input voltage. An additional dummy
switch of the same device with same length but of width W/2
is connected in series to avoid the error induced by channel
injection. When the clk is high, the input voltage is charged in
the capacitor, when the clk is low, it will be discharged to the
comparator in next level. The Track and Hold circuit has been
simulated standalone to measure its performance yielding the
following results.
Fig. 21.
Fig. 19.
Track and Hold schematic
Fig. 20.
Track and Hold symbol
Standalone response of Track and Hold circuit
