ELEC 2441 - Computer

Organization and Microprocessors

(Lecture Note #2B: Basic Organization &

Operations of A Microcomputer)

by Dr. Vincent TAM

* Ref: Chapter 5 & 6 of Microcomputers and

Microprocessors (6th Edition), R.J. Tocci & F.J. Ambrosio,
2003.

Todays Quote

We still do not know one thousandth of one percent what nature has
revealed to us.

- Albert Einstein.

Chapter 2 1
2. Basic Organization & Operations of
A Microcomputer

[Part B]

Objectives:

The Basic Organization of A Microcomputer

(MC68HC11) System;
The Register Set inside the CPU;
The Control Bus Signals;
CPU READ Timing Diagram (considering the
variations of important control/input signals
involved);
Bus Activity during program execution (i.e. detailed
investigation of changing values inside the 3 buses for
executing a fragment of assemble codes);
Memory Map (i.e. basic organization/allocation of
memory blocks/pages for different functions).

Chapter 2 2
The Basic Organization of A Microcomputer
(MC68HC11) System

A number of internal registers are present.

Chapter 2 3
Program Counter (PC)

It is a register that contains the address of the next byte of

an instruction code to be fetched from memory into the
CPU. [Note: a complete instruction code like $9680 in our previous
example always needs 2 or more (1-byte) memory units to store!]

The control unit (i.e. the timing & control logic (TCL))
sends the necessary enable signals to the PC to place the
PC's content onto the address bus.

The PC's content is then automatically incremented to

point to the next byte of an instruction code in memory.

Data Address Register (DAR)

It holds the address of the operand to be fetched from

memory into the CPU. Again the control unit provides the
signals to place DAR's content onto the address bus.

Instruction Register (IR) & Control Unit

To fetch an op-code from memory, the control unit

generates signals to

(i) put the content of the PC (= address of the op-code

byte) onto the address bus, and

Chapter 2 4
(ii) set R/W'=1 (i.e. a high voltage) to initiate a read from
memory.

With the given address, the memory unit gets the op-code
byte from the memory cells, and puts the byte onto the
data bus. The control unit generates signals to copy the
byte into the Instruction Register (IR).

Hence the IR contains the op-code.

The decoder circuit decodes the op-code & signals the

control unit to generate the required sequence of control
signals to complete the execution of the given instruction.

Information about the sequence of control signals to be

generated (called a micro-program) is stored in the control
unit.

Accumulator (A) & Data Register (DR)

The operands to be operated on are read from memory &

copied into these two registers. The ALU then performs
the required operation & the result is put into
accumulator A.

Chapter 2 5
Register set

Name Size Symbol Usage

(bits)
Index register 16 X address information
Index register 16 Y address information
Stack pointer 16 SP stack data structure
Data address register 16 DAR operand address
Program counter 16 PC instruction address
Accumulator 8 A general data
Accumulator 8 B general data
Instruction register 8 IR instruction code
Condition code 8 CCR (details below)
register

Condition code register

S X H I N Z V C
b7 b6 b5 b4 b3 b2 b1 b0

It is also known as the status register or process status

register.

After each instruction execution, the condition bits are set

accordingly.

Chapter 2 6
N-bit is set to 1 if the result, treated as a signed integer, is
negative; otherwise it is 0.

Z-bit is set to 1 if the result is zero, otherwise it is 0.

C-bit is set to 1 if , treating the number(s) as unsigned

integer(s), carry out of (or borrow into) the most
significant bit occurs; otherwise it is 0.

V-bit is set to 1 if overflow occurs, otherwise it is 0.

H-bit (may ignore)

I-bit is the interrupt mask bit. When this bit is set to 1, the
interrupt request (IRQ') input pin is disabled. This bit
can be set or cleared by the SEI and CLI instructions
respectively.

X-bit is the interrupt mask bit. When this bit is 1, the

non-maskable interrupt request (XIRQ') input pin is
disabled. However, most of the time, this bit cannot be set
to 1 by the programmer, hence the name non-maskable
interrupt. The process of setting and clearing this bit is a
little complex.

Chapter 2 7
Control Bus Signals

The control bus consists of the signals R/W', Reset',

XIRQ', IRQ', AS, E.

(1) Read/Write' (R/W', output signal)

This is activated by the CPU to tell the memory or I/O
units whether it wants to read or write. It sets the signal
to 1 for Read and sets to 0 for Write.
Read CPU gets data from memory or I/O unit
Write CPU sends data to memory or I/O unit

(2) Reset' (input & output signal)

In most computers, this is an input only signal. It is used
to reset (boot up) the computer.
It is normally high & is driven low by the external circuit
to initiate a reset sequence.
The Program Counter is initialized to the address of the
first instruction to be executed. When the Reset' signal
returns to high, execution begins.

Chapter 2 8
There are 4 cases for reset. One common case is the

- External reset
When an external circuit pulls this signal low for a
duration of at least 4 E-clock cycles, the processor
executes the reset service routine (the bootstrap
program).

Generally, a bootstrap program does the following:

1. Initialize the CPU registers (stack pointer, etc.)
2. Initialize I/O device control registers
3. Test the RAM
4. Check status of I/O devices
5. Display the system status on an output device (e.g.,
monitor) or prompt for input commands.

(3) XIRQ', IRQ' (input signal)

These are active-low interrupt request signals. When an
I/O device wants the CPU to do something for it (e.g.,
writing/reading a byte to/from the I/O device), it pulls this
signal low.

(4) AS, E (output clock signals)

The E signal is the system clock signal. The frequency can
be up to about 2 MHz.
Chapter 2 9
Besides the E-clock, an internal PH2 (phase 2) clock is also
generated.
The AS signal is used to indicate that the Port C pins are
being used as address pins (when AS =1).

Chapter 2 10
CPU Read timing

Port B : the address port (of 8 pins : A8-A15) of the

processor/MPU;
Port C : the address/data (co-sharing) port (A0-A7 or D0-D7) of
the processor/MPU.

Chapter 2 11
1. At the rising edge of AS (Point 1), the CPU sets R/W' to
1 to indicate read, & puts the address on the pins of
Ports B & C.

2. If the memory read is an instruction fetch, the PC is

incremented at the rising edge of PH2 (Point 2).

3. At the falling edge of AS (Point 3), the address bits A0-

A7 are latched, & the address bus holds the 16-bit
address.

4. At the rising edge of E-clock (Point 4), the selected

memory or I/O device is enabled, & the device begins
putting data onto the data bus. After a while, valid
data appears on the data bus.

5. At the falling edge of the E-clock (Point 5), the CPU

latches the data from the data bus into its internal
register such as the instruction register.

Chapter 2 12
Bus activity during program execution

It is instructive to examine the contents of the address &

data buses during instruction execution.

Let the following instructions be executed.

Assume the initial content of accumulator A is $12.

Memory Content Mnemonic Comments

address
C300 BB ADDA $D75C ;add data from
C301 D7 address D75C to acc. A
C302 5C & put result in A.
C303 B7 STAA $D250 ;store content of acc. A
C304 D2 in address D250.
C305 50
D75C 2A

In the following diagram, 'a, b, c, d, e' marked on the

waveforms correspond to 'Points 1, 2, 3, 4, 5' respectively
in the previous CPU read timing diagrams.

It takes 8 clock cycles to complete the 2 instructions.

Please refer to the textbook for more details.

Chapter 2 13
Chapter 2 14
Memory map
The address space is divided into different ranges, each
range is used for accessing a specific memory or I/O
device.

For example,

In the 64k-byte address space available, 16k is allocated to

address the ROM, 4k to I/O devices, & 8k to RAM. Some
address ranges are not used.

FFFF
ROM
C000

8FFF
8000 I/O

1FFF
RAM
0000

Chapter 2 15
Case Study of A Basic Uni-processor (MC68HC11)
Machine

Let the address space be partitioned as:

FFFF
ROM
C000

8FFF
I/O
8000

0FFF
RAM
0000

The allocation consists of 16K-byte for ROM addressing,

4K-byte for I/O, and 4K-byte for RAM.

Chapter 2 16
Address Decoding Circuit

Let a 64k-byte memory system be implemented by using

16 memory chips of 4k-byte each.

One way is to use the upper 4 address bits (A15-A12) to

select the chip, and the lower 12 address bits (A11-A0) to
address the byte within the selected chip.

Chapter 2 17
Summary: [** The following key points are written to facilitate your revision.
Knowing ONLY these key points is always not sufficient for test or exam.]
The basic organization of the (MC68HC11) microcomputer system
includes the microprocessor unit (MPU) containing the program
counter (PC), data address register (DAR), instruction register
(IR), control unit, accumulator(s) and data register, arithmetic and
logic unit (ALU). Outside the MPU, there are data, address and
control buses carrying different signals to connect the MPU with
other peripheral devices like the main memory (MEM) or I/O
devices;
The register set depicts the set of internal registers inside the MPU
for the normal operations of the microcomputer system. For the
MC68HC11 system, the register set contains : PC, IR, DAR, index
register X & Y (IX & IY), stack pointer (SP), Accumulator A & B
and condition code register (CCR). The CCR will be updated each
time after an instruction is executed;
The control bus consists of the signals: R/W', Reset', XIRQ', IRQ',
AS, E to be used for various functions;
The CPU Read timing diagram shows the 5 key events in each read
operation performed by the CPU/processor: i) generate R/W and
new address; ii) increment PC, iii) full address is latched onto the
address bus; iv) enable the selected device and v) latch data onto
the MPU;
The bus activity of a microcomputer examines the contents of the
address & data buses during the execution of each instruction;
The memory map/system shows how the total memory address
space is divided into different ranges, and each range is used for
accessing a specific memory or I/O device.

Chapter 2 18