The PCI bus
Main features
• coupling of the processor and expansion bus by means of a bridge,
• 32-bit standard bus width with a maximum transfer rate of 133
Mbytes/s,
• expansion to 64 bits with a maximum transfer rate of 266 Mbytes/s,
– PCI-64/66 532 Mbytes/s,PCI-X 64/133 1064 Mbytes/s
• supporting of multi-processor systems,
• burst transfers with arbitrary length,
• supporting of 5 V and 3.3 V power supplies,
• write posting and read prefetching,
• multimaster capabilities,
• operating frequencies from 0 MHz to a maximum of 33 MHz,
– PCI-66 3.3V only, PCI-X 100MHz-133MHz
• multiplexing of address and data bus reducing the number of pins,
• supporting of ISA/EISA/MCA,
• configuration through software and registers,
• processor independent specification
Block diagram of a PCI bus system
Processor/Main Memory System
Copro- Main
CPU Cache
cessor Memory
PCI Motion
Audio
Bridge Video
PCI Bus
SCSI host Interface to LAN Graphics
I/O
adapter Expansion Bus adapter adapter
Expansin Bus (ISA/EISA)
Bus Slot Bus Slot Bus Slot Bus Slot
PCI Chipset on Motherboard
PCI bus
PCI bus Signals
• ACK64 # : acknowledge 64-bit transfer
• AD31-AD0: 32 address and data pins form the multiplexed PCI address and data bus
• C/BE3#-C/BE0#: command and byte-enable
• CLK: PCI clock signal
• DEVSEL#: device select
• FRAME:
• GNT#: grant
• IDSEL: device select during configuration
• INTA#, INTB#, INTC#, INTD#: interrurpt signals
• IRDY#: initiator ready
• LOCK: defines an atomic access
• PAR: even parity for AD31-AD0 and C/BE3#-C/BE0#
• PERR#: parity error
• PRSNT1#, PRSNT2#: indicate that an adapter is installed
• REQ#: request signal to the bus arbitration unit
• REQ64#: 64-bit transfer request
• RST: resets all PCI units
• SBO#: snoop backoff, indicates a hit to a modified cache line
• SDONE: snoop done
• SERR#: system error
• STOP: target-abort
• TCK, TDI, TDO, TMS, TRST#: JTAG boundary scan test signals
• TRDY: target ready
• 64 bit expansion
– AD63-AD32: 32 address and data pins form the expansion of the multiplexed PCI address and
data bus
– C/BE7#-C/BE4#
– PAR64: even parity for the 64bit expansion
The PCI read transfer burst
The PCI write transfer burst.
PCI bus features
• Bus Arbitration
– Parallel arbitration
– Hidden arbitration
– Arbitration algorithm is not defined
• DMA
– Burst transfers
• Interrupts
– INTA# activated
– Data: interrupt vector
PCI Bus Cycles
• INTA sequence (0000)
• special cycle (0001)
• I/O read access (0010)
• I/O write access (0011)
• memory read access (0110)
• memory write access (0111)
• configuration read access (1010)
• configuration write access (1011)
• memory multiple read access (1100)
• dual addressing cycle (1101)
• line memory read access (1110)
• memory write access with invalidation (1111)
PCI Configuration Address Space
31 16 15 0
• Manufacturer ID
64 Byte Header
Unit ID
Status
Manufacturer ID
Command
– allocated by PCI SIG
BIST
Class code
Header Latency
Revision
CLS • Unit ID, revision
– identifies unit
192 Bytes Available
• Class code
for PCI Unit
Base Address register
– type of PCI unit
Reserved
Reserved
Expansion ROM Base Address
Reserved
Reserved
Max. Lat. Min. GNT INT-Pin INT-Line
Status and Command Registers
• Status: • Command:
– PER: Parity error – BEE: Fast back-to-back cycles
– SER: System error (Back-to-Back Enable)
– MAB: Master abort – SEE: SERR Enable
– TAB: Target abort received – WC: Wait cycle control
– STA: Target abort signaled – PER: Parity error (Parity Error
– DEVTIM: DEVSEL timing Response)
• 00=fast 01=medium – VPS: VGA palette snoop
10=slow 11=reserved – MWI: Memory write access with
– DP: Data parity error invalidation
– FBB: Fast back-to-back – SC: Special cycle
cycles supported/ – BM: Busmaster
unsupported – MAR: Activate/deactivate
Memory address area
– IOR: Activate/deactivate I/O
address area
PCI Configuration Address Spaces
• Configuration Mechanism #1
– CONFIG-ADDRESS (0cf8h) and CONFIG-
DATA (0cfch) registers are defined in the I/O
area
31 30 24 23 16 15 11 10 8 7 2 1 0
ECD
Reserved Bus Unit Function Register Type
• Configuration Mechanism #2 (for PC
systems)
– 4k I/O address range between c000h and cfffh
PCI Base Address Registers
For Memory Address Space
31 16 15 4 3 2 1 0
PRF
Base Address Type 0
For I/O Address Space
31 16 15 2 1 0
PRF
Base Address 0
For Expansion ROM Address Space
31 16 15 11 10 2 1 0
AD
Base Address Reserved 0
• PRF: Prefetching not possible/prefetching possible
• Type: Positioning type
– 00=any 32-bit address, 01=less than 1M, 10=any 64-bit address,
11=reserved
• AD: Address decoding and expansion ROM deactivated/
activated
Evolution of PC buses
The PCI Express Bus
• Point to point protocol
– x1, x2, x4, x8, x12, x16 or x32 point-to-point
Link
• Differential Signaling
Electrical Physical Layer Showing
Differential Transmitter and Receiver
PCI Express System
PCI Express Properties
• Packet Based Protocol
• Bandwidth and Clocking
– 2.5 Gbits/sec/lane/direction
– 8b/10b encoding
– 250 Mbytes/sec/lane/direction
• Address Spaces
– Memory
– I/O
– Configuration (extended from 256 Bytes to 4
Kbytes)
PCI Express Transactions
• Transactions
– memory read / write
– I/O read / write
– configuration read / write
– new transaction type: Message transactions
• Transaction Model
– posted (split transaction communication)
– non-posted
PCI Express Properties
• Quality of Service (QoS)
– deterministic latencies and bandwidth
• Traffic Classes (TCs)
– TCs can move through the fabric with different priority
• Virtual Channels (VCs)
– Each Traffic Class is individually mapped to a Virtual Channel
• Interrupt Handling
– Virtual wires
• Power Management
– device power states: D0, D1, D2, D3-Hot and D3-Cold
• D0 is the full-on power state
• D3-Cold is the lowest power state.
– Link power states: L0, L0s, L1, L2 and L3
• Hot Plug Support
• PCI Compatible Software Model
PCI Express Topology
PCI Express Device Layers
PCI Express Transaction Layer Packets
PCI-X-AS (advanced switching) Packet format
The PCI Express AS protocol is inserted into a base PCI Express format. The data
payload, in this case a PCI Express base packet, could be data in any protocol format as PCI
Express AS is protocol agnostic. The PCI Express AS protocol requires a start indicator, or
comma, and an AS header that contains the PI or Protocol Interface and the routing path of the AS packet.
