Computer

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The interconnection structure must support the
following types of transfers:

Memory Processor I/O to or

I/O to Processor
to to from
processor to I/O
processor memory memory

An I/O
module is
allowed to
exchange
data
Processor Processor
directly
reads an Processor reads data Processor
with
instruction writes a from an I/O sends data
memory
or a unit of unit of data device via to the I/O
without
data from to memory an I/O device
going
memory module
through the
processor
using direct
memory
access
A communication pathway Signals transmitted by any
connecting two or more one device are available for
devices reception by all other
• Key characteristic is that it is a devices attached to the bus
I
n
shared transmission medium • If two devices transmit during the
same time period their signals will
overlap and become garbled
n
e
Typically consists of multiple
t
communication lines Computer systems contain a
number of different buses B c
• Each line is capable of
transmitting signals representing
that provide pathways
between components at e
binary 1 and binary 0
various levels of the u t
r
computer system hierarchy

s i
c
System bus
o
o
• A bus that connects major The most common computer
computer components (processor,
memory, I/O) interconnection structures
are based on the use of one
or more system buses n
n
Data Bus
 Data lines that provide a path for moving data among system
modules

 May consist of 32, 64, 128, or more separate lines

 The number of lines is referred to as the width of the data bus

 The number of lines determines how many bits can be

transferred at a time

 The width of the data bus

is a key factor in
determining overall
system performance
+ Address Bus Control Bus

 Used to designate the source or  Used to control the access and the
destination of the data on the use of the data and address lines
data bus
 If the processor wishes to  Because the data and address lines
read a word of data from are shared by all components there
memory it puts the address of must be a means of controlling their
the desired word on the use
address lines
 Control signals transmit both
 Width determines the maximum command and timing information
possible memory capacity of the among system modules
system
 Timing signals indicate the validity
 Also used to address I/O ports of data and address information
 The higher order bits are
used to select a particular  Command signals specify operations
module on the bus and the to be performed
lower order bits select a
memory location or I/O port
within the module
Bus Interconnection Scheme
 C
o a
n t
B
f i
u
i o
s
g n
u s
r
+
Elements of Bus Design
 Timing of
Synchronous
Bus
Operations
 Timing of
Asynchronous
Bus
Operations
+
Point-to-Point Interconnect

Principal reason for change At higher and higher data

was the electrical rates it becomes
constraints encountered increasingly difficult to
with increasing the perform the synchronization
frequency of wide and arbitration functions in a
synchronous buses timely fashion

A conventional shared bus

on the same chip magnified
Has lower latency, higher
the difficulties of increasing
data rate, and better
bus data rate and reducing
scalability
bus latency to keep up with
the processors
+Quick Path Interconnect
QPI
 Introduced in 2008

 Multiple direct connections

 Direct pairwise connections to other components
eliminating the need for arbitration found in shared
transmission systems

 Layered protocol architecture

 These processor level interconnects use a layered

protocol architecture rather than the simple use of
control signals found in shared bus arrangements

 Packetized data transfer

 Data are sent as a sequence of packets each of which

includes control headers and error control codes
 Multicore
Configuration
Using
QPI
QPI Layers
+
Physical Interface of the Intel QPI
Interconnect
+
QPI Multilane Distribution
+
QPI Link Layer

 Flow control function

 Performs two key  Needed to ensure that a
functions: flow control and sending QPI entity does not
error control overwhelm a receiving QPI
entity by sending data faster
 Operate on the level of than the receiver can process
the flit (flow control the data and clear buffers for
unit) more incoming data
 Each flit consists of a 72-
bit message payload
 Error control function
and an 8-bit error
control code called a  Detects and recovers from
cyclic redundancy check bit errors, and so isolates
(CRC) higher layers from
experiencing bit errors
+
QPI Routing and Protocol Layers

Routing Layer Protocol Layer

 Packet is defined as the unit of
 Used to determine the course transfer
that a packet will traverse
across the available system  One key function performed at
interconnects this level is a cache coherency
protocol which deals with
 Defined by firmware and making sure that main
describe the possible paths memory values held in
that a packet can follow multiple caches are consistent

 A typical data packet payload

is a block of data being sent to
or from a cache
+
Peripheral Component
Interconnect (PCI)
 A popular high bandwidth, processor independent bus that can
function as a mezzanine or peripheral bus

 Delivers better system performance for high speed I/O

subsystems

 PCI Special Interest Group (SIG)

 Created to develop further and maintain the compatibility of the PCI
specifications

 PCI Express (PCIe)

 Point-to-point interconnect scheme intended to replace bus-based
schemes such as PCI
 Key requirement is high capacity to support the needs of higher data rate
I/O devices, such as Gigabit Ethernet
 Another requirement deals with the need to support time dependent data
streams
+
PCIe
Configuration
+
PCIe Protocol Layers
+
PCIe Multilane Distribution
 PCIe
Transmit
and
Receive
Block
Diagrams
 Receives read and write requests from
+ 
the software above the TL and creates
request packets for transmission to a
destination via the link layer

PCIe  Most transactions use a split transaction

technique
Transaction Layer (TL)  A request packet is sent out by a
source PCIe device which then waits
for a response called a completion
packet
 TL messages and some write
transactions are posted transactions
(meaning that no response is
expected)

 TL packet format supports 32-bit

memory addressing and extended
64-bit memory addressing
+
The TL supports four address
spaces:
 Memory  I/O
 The memory space includes  This address space is used
system main memory and
PCIe I/O devices
for legacy PCI devices, with
reserved address ranges
 Certain ranges of memory
addresses map into I/O used to address legacy I/O
devices devices

 Configuration  Message
 This address space enables  This address space is for
the TL to read/write control signals related to
configuration registers interrupts, error handling,
associated with I/O devices and power management
PCIe TLP Transaction Types
+

PCIe
Protocol
Data
Unit
Format
+
TLP Memory Request Format