wee vw God ir vw ewe SYLLABUS Microprocessor and Interfacing - (160712) cesis_| Examination Mas | thoy arts Praca Mars ae [see [ raon | ese [ram a | 30 x0 20 10 to Microprocessor. Components of a Microprocessor ; Regsters,ALU and Control & timing, System bus (data, address and control bus), Microprocessor systems swith bus organization. 2, Microprocessor Architecture and Operations. Memory. UO devices. Memory and YO operations. 3. 8085 Microprocessor Architecture, Address, Data And Control Buses, £085 Pin Functions, Demultiplexing of Buses, Generation Of Control Signals, Instruction Cycle Machine Cycles, TStates, Memory Interfacing. 4, Assembly Language Programming Basics. Cia ‘Modes, £085 Instruction Set, Instruction And Data Formats. Writing, Assembling & Executing A Program, Debugging The Programs. Writing 6085 assembly language programs with decision, making and looping using ical and branch instructions. 1es, Developing Counters and Time Delay Routines, Code Conver ns, Addressing 5. 6. Stack & Subro BCD Arithmetic and 16-bit Data opera 7. Interfacing Concepts. Ports Programmable Interrupt Controller 8259A, Programmable Peripheral Interface $2554, ing -Of WO Devices, Interrupts In 6085, 8. Advanced Microprocessors: £8086 logical block diagram, segmentation, Pin fu ‘mode, 20986/80386 - Overview and architecture, Programming model, Data types and Instruction set, segments and its types, segment descriptor, descriptor table and Minimum and maximum selectors. TABLE OF CONTENTS (1-1) to (1-18) 4-2 Chapter-1 Introduction to Microprocessor 1 Introduction. . 1.2 Microprocessor Architecture 1.2.1 Components of Microprocessor AAW 2a zReginers 12:3 Conol and Timings Lowe 1.2.14 itera Data bus 1.3 Operations Performed by Microprocessor. 14 Microprocessor System with Bus Organizatios 3 1.4.1 Central Processing Unit (CPU) 1.4.2 Input/Output Module. 1.4.3 System Bus 14.4 Memory Mpdule... 15 Short Questions and Answei Chapter-2 8085 Microprocessor Architecture (2-1) to (2-24) 2.1 Features of 8085.. 2-2 2.2 Architecture of 8085.. 2.2.1 Register Struc 2.22 Arithmetic Logic Uni 125 onc ett nd McnetEcder 2.24 Address Buffer... 2.25 Address / Data Buffer... 2.26 Inerementer / Decrementer Address Latch 2.2.7 Interrupt Contra 2.28 Serial! / 0 Control ———2.2.9 Timing and Control circuitry 27 2.2.10 struction Execution and Data Flow in SES, 127 5 2-8 23.1 Power Supply and Frequency Signals 128 23.2 Data Bus and Adres Bus 2-10 23.3 Controland 2-10 23.4Interope 2 2.5 Short Questions and Answers. ee Chapter -3 8085 - Instruction Cycle, Machine Cycle and T-States 3.1 Timing and Control 3.1.1 8085 Machine Cycles and thel 3.1.2 Concept of Walt States. 3.2 State Diagram of 8085... 3.3 Timing Diagrams for 8085 Instructions... 3.4 Short Questions and Answers. Chapter-4 — Memory Interfacing (4-1) to (#- 22) 4.1 Introduction.. snl 4.2 Terminology and Oper 4.3 Memory Structure and its Requirements. 4. Basle Concepts in Memory Interfacing with 8085... 4.4. interfacing Examples 45 Short Questions and Answers Cflapter-5 8085 Instruction Set and ALP 5.1 Instruction Cia 5.2 Instruction Set of 8085 5.2: Data Transfer Group 5:22 Arithmetic Group 5.2.3 Logie Group 5.2.4 Rotate Group, 5.2.7 Input/Out : 5.2.8 Machine Control Group... 5.3 Addressing Modes... 5.4 Assembly Language Programmi 5.4 Machine Language . 5.4.2 Assembly Language .. 5.4.3 High-level Language . 5.4.4 Assembly Language Program to Machine Language Program 5.45 Storing Hex Code in the Memory 5.4.6 Executing the Program... 5.5 Programming Examples 5.6 Instruction Comparisons... 5.7 Instruction Formats sn '5.8 Short Questions and Answers. %Lab Experiment 6.8 8: Find he Ye Lab Experiment 55.10: Find the 2's complemer Lab Experiment 5.11 Pack the wo unpace BCD ners Leb Experiment 58.12 - Unpack he BCD number Lab Experiment 55.13: Sample subroutine program. Lab Experiment 68.14: Ad contents of two memory locatons Lab Experiment $5.15: Lab Experiment 55.18, Lab Experiment 55.17 Lab Experiment § 5.18 La Experiment $5.19 Lab Experiment 5.520: Si Looping, Counting, Time Delays and Code Conversion (6-1) to (6-60) Chapter - 6 6.1 Looping, Counting and Indexing.. 6.2 Timers 62. 6.2.2 Timer Delay using Counters 6.2.3 Timer Dela mer Delay using NOP Instruction... ing Nested Loops 6.3 Code Conversion, 6.3.1 BCD to Binary Com 6.3.2 Binary to 8CO Com 63.3 BCD to Seven Segment Conversion .. 6.3.4 Binary to ASCII Code Conversion .. + Calculate the sum of series of numbers Data transfer from memory block Bt o mer {ab Experiment 6.13: up te @it mumble A: Divide 16-6 eunborby Bit eumber, 5: Fad te negative numbers ina back of Transfer conents o verapring ply two alg bit pubs wth shit and add method Divide 16-bit number wih 8-tunbar Using siting tachi 13: White an assembly language preg Program to evaluate a? +0?.. zn Program oun given dla ina et of numbers rogram o mull two 16-bit numbers 2 Lhe Exyetiment 8.22: Generate and La Experment6.29: Generste and ceplay 8CO vp coun ith quency to BOD conversion... segnent codes for gwen rumbers. Lab Experiment 6.4.2: Add two 4- = se ‘The latching of lower half of an address is di : ; fan address is done by using © signal from 8085. The Fig. 243 shows the sone can use output of bus. to OOOOH which causes the 8085 to execute the first instruction from address 0O00H. For proper reset operation reset signal must be held low for at least 3 clock cycles. The power-on reset circuit can be used to ensure execution of first nares 75K ewe Fig. 244 Power on reset Fig. 243 Latching circuit TECHICAL PUBLICATIONS? - Ao up teat fy knoe 8085 MereprosessorAchtectire coprocessor and Intetcing 218 FEE Generation of Control Signals leroprocessor provides RD and WR signi ignals The Because these (Memory Weite):T ior (WO Read): To JOW = WO Write): To Fig, 245 and 2.46 show the circuit which get ese ee NE ee TECHICAL PUBLICATIONS?» Anup tt er HocuttMerprocessor and interfacing oR ADR Slells +109 WR+ 10M RD 1 a ion never RD and WR | ee | [Rocio ha ° 1 1 feats 5 a i o 1 ks 1 ii ae baa a t s “Conds = Condition never exist, tease RD ae WR sgals doesnot > low sinalancrs Table 244 Same truth table can be implemented using 3 : 8 decoder as shown in Fig. 247. TECHNICAL PUBLIGATIONS® - Anup tut fer kraeoge a 9085 Miroprcessor Architecture Miroprocessor and interfacing | Ball 1 31 al Fig. 247 Generation of control signais using 3: 8 decoder EXEL bus Drivers Typically the 888 buses can source 400 tA and sink 2 mA of current dain ety one TTL lord, Therefore, i is necessary to increase driving capacity of the S085 bees Bus dives, Buffers ar used to increase the driving capacity ofthe Buses. it can Unidirectional Buffers : ‘As we know, the address bus is ‘unidirectional, bit unidirectional buffer, 7ALS244 is used to buffer higher address bus. The Fig. 24.8 shows the 1LS244. It consists of, testate outputs. Each one can sink 2A mA and source 15 mA of cuszent. These bers ate divided into to groups. The enabling and disabling of these groups aze controled by TG and 2G lines. 2 |e |e |e de Fig. 248 Logie diagram of the 7ALS244 TEcHWCs: PUBLICATIONS® «An up tvs for kowtadepits aah = ered racing 2.18 8085 Mioprocessor Architecture Bi-directional Butfe To incr shows the transceivers tri-state output. Th high, data flows from ‘The active low enable Each buffer in this dev fe baste Aaa A Saute Boa sprocessor to memory or 1/0 device performing TECHNICAL PUBLICATIONS « An up that for knowledge Meoprocessor and Interfacing Fig. 2.440 Typlal 8085 configuration wat peel 065 wots? SATA TECHNICAL PUBLICATIONS® «An vp tt fr hoowndgeMeroprocessar and Interfacing 25 EEE air eg a_i 2. Define the following : 1) Buffer 2) Line drive. GE 5 What conta sigae? Hw ae they seed? RET 4 Gevert cota igang NAND gate. Eo 5 6 Barkin the ned te demaliple hehe ADp- AD, TST Asner the question in brief 805 - Demlipesing ofthe bus AD, = AD SRE ETA Explain how addressidta lines ADpAD, ere de control signals MENIW, MEMR, LOW and JOR fon 10, exe Draw lie digram to generate 8 Draw schematic to generate readfrite cotrl signals for memory icropoceer. 2 10. Explain the role of elok im mionprocessor EB] short questions and Answers G1 List the 16 - bit registers of 8085 microprocessor. ‘Ans. Stack pointer (SP) and Program counter (PC), 2 List the alowed register pairs of 2085, DEE register pair, HL register pair 3 Montion the purpose of SID and SOD tines, ‘Ans. : BAC register pair, ‘Ans. : SID (Serial input data line): It is an input line through which the microprocessor accepts serial data. SOD (Serial output data line): It is an output line through which the microprocessor sends output serial data, 4 What is the function of IO/Mf signal in the 085 7 ‘Ang. : Itis a status signal. It is used operations. When this signal is operations. When this signal is high (1O/M = 5 What Is the signal classification of 8085 7 All the signals of 8085 can be classified into six groups ween memory locations and 1/0 denotes the memory related it denotes an 1/0 operation. Ans. : 8) Address busi) Data bus {if) Control and status signals iv) Power supply and frequency signals +) Externally initiated signals vi) Serial 1/0 ports TECHNICAL PUBLICATIONS® - An up thrust for knowledge 8085 Mcroprocessor Archery eroprocessr and nterfoord er? ‘se of bidirectional butt what te the ute of the driving capacity of the data bus. The data bus of a erease the dsivin onal, s0 i requires a bi-directional bufer that allows ans. Tt is microcomputer system is bidirect the data to flow in both directions: HOLD, READY and SID. 7 Explain the signals HOLD indicates that a peripheral such as DMA co is requesting the Ans. ” " a eees bus, data bus and contol bus, READY is used ponding peripheral is resdy f0 send or accept dats, f ALE sk 8 What Is the need for ALE : 1e ALE signal is used to demultiplex (separate) ADp , (data lines). The separation of address AD, lines and enabling the latch when Ans. (addres lines) and Dy ~ ‘achieved by connecting a external latch to ADy = ALE signal is active. 09. How performance of a microprocessor Is measured Interms of MIPS 7 ‘microprocessor is measured interms of MIPS (Million Instructions per Second). Its given as, 1 MIPS rate = dns. + By replacing the crystal of double frequency than that of existing one we can execute the same instruction in halftime. 1 i 2 5 Mhz crystal is connected with 8085; what Is the value of system clock frequency and one Tatate ? fns.: System clock fequeney = Coal frequency one Tstate = —1 25x10 SMH2 95 Miz, = 0 psec. 42 To obtain a 320 ns clock, what should be the input clock frequency 7 What Is the frequency of clock signal at CLK OUT 7 Ans. T= 320 nsec 1 3a0x10-F 4 St lok equency «= = sa2s Mite, TROHVICAL PUBLICATIONS? «an uo thst for hnomedyeMezoprocessor and inetacing 22 0085 MirprocessrArhitcture Cajal requeney Ge apa oqueng) = Bx Sytem Gack Requeney = 2x3.125x10° = 6.25 MHz 7 guy ef ce sig cx our « SE 625Mtie 2 Important cont slgnals In 8085 microprocessor? Nportant control signals in 8085 microprocessor are : ALE, 10/M, KD = 3125 MH. peripherals to the microprocessor, Q.16 List the five Intorrupt pins available in 8085, ‘Ans. : ‘The five interrupt pins available in 8085 are : TRAP, RST 7.5, RST 65, RST 55, and INTR, 27 _Specty the sizeof dt, adress, memeny word and memory c4picy of 6085 ‘microprocessor. ‘Ans. : Size of data bus = S-bits Size of address bus = 16-bits + Size of memory word = Sits Memory capacity = 64 Kbytes Q18 List the special purpose registers of 8086, ‘ans. : The special purpose registers of 8085 are: 1A (Accumulator) 2. Flag register 3. Instruction register 4, Program counter 5. Stack pointer. als provided for DMA operation by 8085 and explain their use. another m indicates bus and control bus. HILDA : This active high signal is used to acknowledge HOLD request. requesting for the use of the content of PC and INTE flag after reset ? PC is loaded with 0000H and INTE fag is cleared. the need of bus drivers ? fans. Typically, the 85 buses can source 400 WA and sink 2 mA of current, je. it-can drive only one TTL load. Therefore, it is necessary to increase driving capacity of the ‘085 buses. Bus drivers, bulfers are used to increas the driving capacity ofthe buses, 22 What aro the various flags used In 8085 7 ‘Ans. Various flags in 8065 are: (Sign lag), Z (Zero flag), AC (Ausiliany carry flag), P (Parity lag), and CY (Carry fag) Z aoa TECHNICAL PUBLICATIONS® An up true fo knowtadge TTECHRUCAL PUBLICATIONS® - An up thst fer Knowledge8085 - Instruction Cycle, Machine Cycle and T-States Contents 3.1 Timing and Contro! Summer-03,04,06,14,15,17,18, Winter-12,16,18,19, - 3.2. State Diagram of 8085 ............. Summer-04, 3.3 Timing Diagrams for 8085 Instructions .., Summer-03,06,08,13,14,15,16,17,18,19, Winter-14,15,16,18,19, Marks 10 3.4 Short Questions and Answers @-1)‘Mereerocessct and interfacing 3-2 _ 8085. insiuction Cyto, Machine Cyto and T-Sttes EXE timing and Control EEE data in or out of the required, Each machine cycle consists of 3 to 6 clock Therefore we can say that, one i and one machine cycle consists six clock periods, as shown in the Fig. 31.1 Instucton eye ! T l Machine oie 1 Machine oye 2 Macnine eye 5 Testate 1 Testate2 type as shown in Table 1 le and remained v. TECHNICAL PLBLEATIONS® - Anup ba oni Mirorocessor and ntetacing 3-3 8085 (nsructon Oye, Machine Cyee and T-Stalos Representation of Signals Before going to see the timing diagram, we will see the signals and their representation used in the timing diagrams. . then the signals are Jock signal should be square wave with zero rise time an ma with finite rise and Fig. 31.2 shows the practical way of representing clock signal. AAA rae = a (6) Practical lock signal representation time and fall time, as shown in the Logie presentation Group of signals is also called a bus eg. address bus and data bus. To avoid complica ing diagram these signal are grouped and shown in the form of Blok as shown in Big. 314 ST ease wf 4 Group of signals representation TEGHNIGAL PUBLICATIONS® - Anup thst for knowadge3-4 €085- insovcton Ota, Mactine Cyl and TSttes In the group representation individual state is not considered, considered. Change in state of single by the cross as shown the Fig. 314. The tr by dotted lines. Two straight lines represent vi In microprocessor systems, activation of signal/signals depends on the ‘ignal/signals. Such situations are shown in the timing diagrams with specific symbols. There are four possiblities: =A ignal with the change in state of other signal with the change in state of other signals. TECHNICAL PUBLICATIONS® An up tut for knowoeo0 ‘we understand rae Fecion explana when the signals are activated and f pel active state ALE (Address Latoh Enable) state of each in the beginning of the Ty 1 eis acvated in me ne ne, ee TECHNICAL PUBLICATIONS® An up thus for knowdgeMeroprocessor ang intetocing 2:6 _8085- Insuaton Gyele, Machine Cele and T-Stalas To read data from memory or 1/0 device. After selection, devi the data bus with zero access time. ‘Ag Ags (Higher Byto Address) : ‘The higher byte of address is available on the Ag ‘Ty-states of each machine cycle, except bus idle machine I bus during Ty, Ty and as shown in Fig. 319. Fig. 24.9 Wighor byt adérns on Aig lof, Sy 84: ‘These signals are called executed, They a remain active til the end of the machine cycle. nha TECHNICAL PUBLICATIONS® - Anup thst for knowedge nd intracing 3-71 €085- Instucton Gye, Machine Cyele ond T-Siates er When RD signa is acve, dats on memory or 1/0 device to the miroprocetsor, and when WR signal om microprocessor tothe tmemory or 1/0 device, Boh time. 6085 takes place duing Ty and Ty these signals are as shown in the ig 3.1 signals are never acti As we know data activated during Ty and 1 reateyse —b-_—_—§ wie ee —— KERRI 2085 Machine Cycles and thel ‘The OSS has even mache sles. These are LOpeode fetch 2 Memory read 3. Memory wite 5.1/0 write 6 Interrupt acknowledge varies from 4T ‘per the instruction. The following section describes the opcode fetch cy: laces the contents of program counter on the lines, The low-order |AD; lines which st only during Ty. Thus "ALE (Address Latch Enable) which is used to latch the the address in external latch before it disappears. low-order byte low-order byte of eee TECHNICAL PUBLICATIONS® - Aa up thrust fr krowedeMiroprocessor and inter tecing 3:8 _$085-Instueton Cycle, Mache Cyls end F-States (Grepecined| pea fateh ae i +4 | f 10/20.) en tn 7 7 [Xcorowe})-( Cir { \ sia onl aux As iy a Ale Nae As] Date bue TECHNICAL PUBLICATIONS® - An up thus! or none i i z t (©) Opcode fetch machine cyclo (2) Data (opcode) flow from memory to micrprocessor Fig. 3.12 _Miprocessor and Interfacing 3-9 _8085-nsnetion Cyie, Machine Cyclo and T-Statos als 10/7, Sy, and Sp. 10/4 specifies whether its a is tead/ write operation: S; and tion, or whether it =i », opcode fetch, or machine cycle status signals are : 10/M= 0, Sy ww-order address disappears from the ADs - AD; lines. ‘eailable as they were latched during Ty). In Ty, 8085 sends the addressed memory locaton. The memory device then places ldessed memory lecation on the data bus (ADp ~ ADr)- (tate T,)_During Ty 8085 loads the data from the data bus in its Instruction and raises RD to high which disables the memory device executed in Ty For example : MOV A, B, ANA D, ADD B, INR L, DCR C, RAL and many more, Note: For one byte instructions which operate on eight bit data, data is always available in the internal memory of 8085 ic. registers. Step 5 : (State Ts and T,) Ty and Ty wh .4, are used for internal microprocessor operations required by the instruction. and Ty, 8085 performs stack write, intemal 16 bit, and conditional retum operations depending upon the type of instruction. One byte 6 bit operand) are executed in T; and Ty, instructions those operate on sixteen Bit For example DCX H, PCHL, SPHL, INX H, etc. 2, Memory Read Cycle ‘The 8085 executes the memory read cycle to read the contents of R/W memory or priate for memory read machine cycle are issued in Ty. The following section describes the memory read machine cycle in step by step manner. TecHeaL eusLIcaTIONS® - Anup tus or Knowledgespect] X Xe \ VTA (0) Opcode foteh maching cycle (2) Data (opcods) flow from memory to mlcrprocessor 3-2 _8085- nsructon Cj, Machoe Oye nd Tatas Fig. 31.92 teroprocssor and intetecng £085 Insiucton Cys, Machine Cie and T-Satos nd §) 10/M specie wh iis read/ wt ope cfc machine ile operation, oF whether ldeessed memory location on the data bus (ADy - AD;). ind Ty, when entered, are used for intemal microprocessor operations required by the instruction. During Ts and Ty, 8085 performs stack write, internal 16 bit, the type of instruction. One byte operand) are executed in Ts and T,, TECHNVEAL PUBLICATIONS® » As op Brut tna TECHWUCAL CURLICATIONSY An up Dr! fr Kronatomnouy 84 dh Ue» SNOULYONGNA THOIMHORL toe ua dh uy - gSNOUYONNd TOMO fe erry Read ———"1 aes DX | omen Ae AD}-ADs 1015.55 (0) Memory read machine cycle fe Morey vite ———4 ms 7 rss DX ea ares 104-05 [Xana YX baa rom ay tL ata bes = ingens data flow, ~~ Indcates acess Now {) Date flow microprocessor to memory Fig. 3.1.16 Ace) (8) Memory write machine eyele BSL Pm BIS wen WS USI“ OT-E Tie a “Fae poe Reva Gamage oto ooey WF wopanaeu-Se08Meroprecessor and hterteng 312085. Inston Cyl, Machina Cycle and T-Staee Mespresesserandinttueng a 1285 nsucton Cyl, Machine Cyl and T.Satos Step 1 : (State Ty) In T, state, microprocessor places the address on the address lines from stack pointer, general purpose register pair or program counter and activates ALE signal in order to latch low-order byte of address. During Ty, 8085 sends status signals: 10/M1 machine cycle. = 1, and $= 0 for memory read 2; (State T,) In Ty, 8085 sends RD signal low to enable the addressed memory location, The memory device then places the contents of addressed memory location on the data bus (AD) -AD}). Stato Ts) During Ty, 8085 loads the data from the data bus into specified CD, EH, and L) and raises RD to high which disables the memory 3, Momory Write Cyclo ‘The 8085 executes the memory write cycle to stack memory. The length of this machine cycle ‘yee, processor places the address on the address lines purpose register pair and through the write process, st 14 (See Fig. 3.1.14 on previ 1¢ cycle. The memory iagram, except that instead o the data into data memory or 1 - Ty: machine similar to the ‘goes low during T; 5, = 0, $= 1. The step by step manne. Stop 1: (St y stack pointer or general purpose register ps low-order byte of address. During Ty, 8085 IO/M = 0,5; = Oand S) = 1 for memor Stop 2: Tq) In Ty, 8085 places dat for writing into the addressed memory location. e 8035 places the address on the adress lines from and activates ALE signal in order to latch signals : te machine eyele the data bus and sends WR signa low 15 Ty, WH signal goes high, which disables the memory device operation. 4,8. 0 Read and UO Write Cyel The 1/0 read and 1/0 write m memory write machine cyel ead and 1/O write machi operation. Fig. 31.15 (b) and Fi 1/0 write cycles, respectively ine cycles are similar to the memory read and except thatthe 10/M signal is high for 1/0 . High 10/4 signal indicates that itis an 1/0 3.116 (b) show the timing diagrams for 1/0 read and TECHNICAL PUBLICATIONS? An up tnt or Inawiedge _ Meroprocessor and Intertaing 2-19. 085 Inhuetn Cele, Mechine Cyele and States I Z 4 8 & = : 3 ELA i i : 2 3 8 3 Wy | pale h ly 2¢ z 8 2 =m indents adaross flow —= incates data fom, (2) Dataflow from input device to microprocessor Wo. ead eee TECHNICAL PUBLICATIONS® - An up thru for KroneeyeMerete and iter i cng 3-14 _8085- Inston Cyt, Machine Oye and T:Siates roprocessor and Interfacing ‘9:18 0085~Instuetion Oyte, Machine Cyto and T-Sites 6. Intorupt Acknowledge Cycle | acknowledge machine cycle to e| In response to INTR 8 tes interpt es S read an instruction from the & i 2 ag i [a i =| Ps i instructions i i 1 AST Instuton 2 Interrupt Acknowledge Cycle f as g g ing di the interrupt acknowledge machine cycle and = 5 Fig. 3.17 shows the timing diagram of the intent a apes to the opcode Py g of RST instruction. The interrupt acknowledge cycle | a with two exceptions _ 5 Beane go 2 f ¢ | 7 fog hn le |e ai evox LAA UE Ach TREE 4 190} 12 as r ig we The | iz | lit = | ai) 2 108s, 8. 2 BEI [eam EEL ) ; tay ey . 18 1. 'e = i 26 ae Fig. 2447 Resta instruction i a = 4 1. The INTA sig tivated insteed of the RD signal. et] 4 2. The status Mi, Sp and S,) are 111 instead of O11. * = During interrupt acknowledge machine cycle (M,), the RST is decoded, which inate 1 byte CALL instruction to the specific vector location. The machine cycles Mz and My are memory write cyles that store the contents ofthe program counter on the stack, and then a nev instruction cycle begins. TECHINGAL PUBLCATINS® - A vp hast for rote TECHNICAL PUBLEATIONS® a up owe |