System Verilog
OPERATORS,
SUBPROGRAMS
Operators
Included from Verilog
Arithmetic + - * / % **
Logical ! && ||
Relational > < >= <=
Equality == != === !==
Bitwise ~ & | ^ ~^ ^~
Reduction & ~& | ~| ^ ~^ ^~
Shift >> << >>> <<<
Concatenation { op1, op2, op3, .. , opn }
Replication { no_of_times { a } }
Conditional cond ? True_Stm : False_Stm
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Operators
Additions to System Verilog
Arithmetic += -= *= /= %=
Increment/Decrement ++ --
Logical -> <->
Bitwise &= |= ^=
Shift >>= <<= >>>= <<<=
Wildcard Equality =?= !?=
Set Membership inside
Distribution dist
Stream {<<{}} {>>{}}
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Example1
int a, b, c=2, d=6, e=10;
initial begin Result:
a=d++; a=6
b=++d; b= 8
c*=d; c= 8
c>>=1; d= 8
e%=3; e= 3
e+=2;
end
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Example2
a->b is same as !a || b
a<-> b is same as (!a || b) && (!b || a)
int a=1, b=2;
initial begin
Result:
if(a->b)
a implies b
$display(“a implies b”);
a is logically equivalent to b
if (a<-> b)
$display(“a is logically equivalent to
b”);
end
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Example3
int i=11, range=0; Result:
bit a=5’b10101; range=2
initial begin
if(i inside { [1:5], [10:15], 17,18}) // i is 1-5 or 10-15 or 17or 18
range+=1;
if(a=?=5’b1XZ01) //X and Z acts like don’t care
range+=1;
end
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Loops
Included from Verilog
o for
o repeat
o while
Additions to System Verilog
o foreach
o do while
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Loops
inital begin
int i=10;
inital begin
do begin
int a [8] [5];
i -=1; //statements
foreach ( a [i, j] )
end
a[i] [j]=$random;
while (i >5)
end
end
Used to access all Statements executed first an
elements in an then execution depends upon
array condition
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Break and Continue
inital begin inital begin
int i; int i;
repeat(10) repeat(10)
begin begin
if(i==7) break; if(i==7) begin continue;
i+=1; i+=1; end
end end
end i+=1;
Result: i=7 end Result: i=7
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package
Packages provide ways to have common code to be
shared across multiple modules.
A package can contain any of the following:
o Data Types
o Subprograms (Tasks/Functions)
o Sequence
o property
Elements of a package can be accessed by:
o :: (Scope Resolution Operator)
o import keyword
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`include vs import
`include is used to include the content of specified file to
the given location.
It is equivalent to copying the content and pasting at the
given location.
`include “xyz.v”
Import is used to access elements defined inside the
package without copying them to current location.
import :: element_name;
import :: *;
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Example
“[Link]” `include “[Link]”
function int add (input int a, b ); `include “[Link]”
add= a + b; module test;
endfunction initial begin
int x=add(1, 2, 3);
“[Link]” int y=add(3, 4);
function int add (input int a, b, c end
); endmodule
add= a + b + c;
Compilation error add already
endfunction exists
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Example
“[Link]” “[Link]”
package mypack1; package mypack2;
int x; int y;
function int add (input int a, b ); function int add (input int a, b, c
add= a + b; );
endfunction add= a + b + c;
endfunction
endpackage
endpackage
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Example
`include “[Link]”
`include “[Link]”
module test;
import mypack1::*;
import mypack2::*;
initial begin
x=mypack1 :: add(3, 6); //x=9
y=mypack2 :: add(4, 5, 3); //y=12
end
endmodule
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Type Parameter
A parameter constant can also specify a data type.
This allows modules, interfaces, or programs to have
ports and data objects whose type can be set for each
instance.
module test #( parameter p1=1, parameter type p2= logic)
( input p2 [p1:0] in, output p2 [p1:0] op);
p2 [p1:0] x;
endmodule
test #(15, bit) u0 (a,b); //Module instance example
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Subprograms
Following advancement has been done to System
Verilog Subprograms (Functions and Task) :
o Default Port Direction : default port is input, unless
specified. Following types of ports are allowed:
o input : value captured during subprogram call.
o output: value assigned at end of subprogram.
o inout : value captured at start assigned at the end.
o ref : a reference of actual object is passed, the object
can be modified by subprogram and can also respond
to changes.
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Subprograms
Following advancement has been done to System Verilog
Subprograms (Functions and Task) :
o Default Data Type : Unless declared, data types of ports is
logic type.
o Default Value : Input ports can have default values. If few
arguments are not passed, there default values are taken.
o begin..end : begin end is no longer required.
o Return : return keyword can be used to return value in case of
functions and to exit subprogram in case of tasks.
o Life Time : Variables can be defined as static or automatic.
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Function and Tasks
Both Functions and Tasks can have zero or more
arguments of type input, output, inout or ref.
Only Functions can return a value, tasks cannot return a
value.
A void return type can be specified for a function that is
not suppose to return any value.
Functions executes in zero simulation time, where as
tasks may execute in non zero simulation time.
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Example1
function int add (int a=0, b=0, c=0);
return a + b+ c;
endfunction
initial begin
int y;
y=add(3, 5); //3+5+0
#3 y=add(); //0+0+0
#3 y=add(1, 2, 3); //1+2+3
#3 y=add(, 2, 1); //0+2+1
end
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Example2
function void display (int a=0, b=0); //void function
$display(“a is %0d b=%0d”, a, b);
endfunction
initial begin
display(3, 5); //a=3 b=5
#3 display(); // a=0 b=0
#3 display(1); // a=1 b=0
#3 display( , 3); // a=0 b=3
end
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Example3
function int initialize(ref int a [7:0]);
foreach( a[ i ] )
a[ i ]=$random;
return 1;
endfunction
int b[7:0], status;
initial begin
status=initialize(b); //same as pointer concept in c
#3 void’(initialize(b)); // ignore return value
end
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Example4
//If argument is const then subprogram cannot modify it
function void copy(const ref int a [7:0], ref b [7:0]);
foreach( a[ i ] )
b[ i ]=a[ i ];
endfunction
int a[7:0], b [7:0];
initial begin
foreach (a [i] ) a [ i ]=$random;
copy(a, b);
end
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Example5
task check (int a, output b);
if (!a) begin
b=1;
$display(“error”);
return; end
b=0;
endtask
initial begin
#3 check(5, error); // error=0
#3 check(0, error); // error=1
end
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Example6
task add (int a=0, b=0, output int z); //Variables are static by
//default
#2 z=a + b;
endtask
int x, y; Result
:
initial fork x=6
add(3, 5, x); y=6
#1 add(2, 4, y);
join
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Example6
task add (int a=0, b=0, output int z); //Variables are static by
//default
#2 z=a + b;
endtask
int x, y; Result
:
initial begin x=8
add(3, 5, x); y=6
#1 add(2, 4, y);
end
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Example7
task automatic add (int a=0, b=0, output int z);
#2 z=a + b;
endtask
int x, y;
Result
initial fork :
add(3, 5 , x); x=8
#1 y=add(2, 4 , y); y=6
join
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