EC – 403 | VD
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Experiment - 1
Aim: Write Verilog codes for all basic logic gates having structural, data flow
and behavioural model and
perform synthesis by generating different synthesis and timing waveforms.
Software : Vivado
Theory:
The basic logic gates are categorized into seven types as AND, OR, XOR, NAND, NOR,
XNOR, and NOT. These
are the important digital devices, mainly based on the Boolean function. Logic
gates are used to carry out the
logical operations on single or multiple binary inputs and result in one binary
output.
(1) OR Gate:
The OR gate output attains the state 1 if either one or more inputs attain the
state Boolean expression of OR gate can be
given by,
Y = A + B
(2) AND Gate:
In an AND gate, the output attains state 1 if and only if all the inputs are in
state Boolean expression of AND Gate can be
given by,
Y = A . B
(3) NAND Gate:
It's a digital circuit with two or more inputs that creates an output that's the
logical AND of all those inputs inverted.
Y = ~(A.B)
(4) NOR Gate:
It's a digital circuit with two or more inputs that creates an output that's the
logical OR of all those inputs inverted.
Y = ~(A + B)
(5) XOR Gate:
The Exclusive-OR gate is known as the XOR gate. XOR is a digital logic gate that
gives a true (1 or HIGH) output when
the number of true inputs is odd.
Y = A^B
(6) XNOR Gate:
The XNOR gate is a digital logic gate whose function is the logical complement of
the Exclusive OR (XOR) gate.
Y = ~(A^B)EC – 403 | VD
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Truth Tables:EC – 403 | VD
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Code :
(1) Structural
module basic_gates
( Input A_05,B_05
output C0,C1,C2,C3,C4,C5
);
AND(C0,A_05,B_05);
OR(C1,A_05,B_05);
NAND(C2,A_05,B_05);
NOR(C3,A_05,B_05);
XOR(C4,A_05,B_05);
XOR(C5,A_05,B_05); endmodule
(2) Data Flow
module half_adder( input
A_05,B_05
output C0,C1,C2,C3,C4,C5
);
ASSIGN C0 = A_05 & B_05;
ASSIGN C1 = A_05 | B_05;
ASSIGN C2 = ~(A_05 & B_05);
ASSIGN C3 = ~(A_05 | B_05);
ASSIGN C4 = (A_05 ^ B_05);
ASSIGN C5 = ~(A_05 ^ B_05);
endmodule
(3) Behavioural
module HALF_ADDER_behavioural(
input A_05,B_05
output C0,C1,C2,C3,C4,C5
); always @(A_05,
B_05) begin C0 =
A_05 & B_05;
C1 = A_05 | B_05;
C2 = ~(A_05 & B_05);
C3 = ~(A_05 | B_05);
C4 = (A_05 ^ B_05);
C5 = ~(A_05 ^ B_05);
end endmodule
Schematic :
A_05
B_05EC – 403 | VD
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Simulation:
1 . Functional Verification
2 . Post Synthesis
A_05
B_05
B_05
A_05
A_05_IBUF
B_05_IBUFEC – 403 | VD
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3. Post Implementation
5. Utilization
On performing this practical, we observed schematic of different basic gates as
well as behavioural simulation, post
synthesis, post implementation waveforms respectively. Moreover, we also observed
its power output and time
utilization.
4 . Power
CONCLUSION:
A_05
A_05_IBUF
B_ 05_IBUF
_05
B _05
A_05
A_05
A_05
A_05
A_05
A_05EC – 403 | VD
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Experime nt – 2A
Aim: Write Verilog codes for implementing half-adder having structural, data flow
and behavioral model and
perform synthesis by generating different synthesis and timing waveforms.
Software : Vivado
Theory:
A full adder is a digital circuit that performs addition. Full adders are
implemented with logic gates in hardware. A
full adder adds three one-bit binary numbers, two operands and a carry bit. The
adder outputs two numbers, a sum
and a carry bit. A full adder takes two binary numbers plus a carry or overflow
bit. The output is a sum and another
carry bit. Full adders are made from XOR, AND and OR gates in hardware.
Code :
(1) Structural
module half_adder_struct
( input
A_05,B_05 output
SUM,CARRY
);
XOR(SUM,A_05,B_05);
AND(CARRY,A_05,B_05) endmodule
(2) Data Flow
module half_adder( input
A_05, B_05 output
SUM,CARRY); assign SUM =
A_05 ^ B_05; assign CARRY=
A_05 & B_05; endmodule
(3) Behavioural
module HALF_ADDER_behavioural(
input A_05, B_05 output reg
SUM, CARRY); always @(A_05,
B_05) begin
SUM = A_05 ^ B_05;
CARRY = A_05 & B_05;
end endmoduleEC – 403 | VD
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Simulation:
1 . Functional Verification
2 . Post Synthesis
3 . Post Implementation
A_05
B _05
A_05
B _05
A_05_IBUF
B _05_IBUF
A_05
A_05_IBUF
B _05
B _05_IBUFEC – 403 | VD
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4. Power
Conclusion:
On performing this practical, we observed schematic of half adder as well as
behavioural simulation, post
synthesis, post implementation waveforms respectively. Moreover, we also observed
its power output and time
utilization.
5 . UtilizationEC – 403 | VD
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Experiment – 2B
Aim: Write Verilog codes for implementing full-adder having structural, data flow
and behavioral model and
perform synthesis by generating different synthesis and timing waveforms.
Software : Vivado
Theory:
A full adder is a digital circuit that performs addition. Full adders are
implemented with logic gates in hardware. A
full adder adds three one-bit binary numbers, two operands and a carry bit. The
adder outputs two numbers, a sum
and a carry bit.
A full adder takes two binary numbers plus a carry or overflow bit. The output is
a sum and another carry bit. Full
adders are made from XOR, AND and OR gates in hardware.
Code :
(1) Structural
module full_adder_struct
( input
A_05,B_05,CIN_05,
output SUM,CARRY
);
wire x_05,y_05,z_05;
xor(SUM,A_05,B_05,CIN_05);
and(x_05,A_05,B_05);
and(y_05,B_05,C_05);
and(z_05,A_05,C_05);EC – 403 | VD
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or(CARRY,x_05,y_05,z_05);
endmodule
(2) Data Flow
module FA_Dataflow( input
A_05, B_05, CIN_05,
output SUM,CARRY);
assign SUM = A_05 ^ B_05 ^ CIN_05;
assign CARRY= A_05 & B_05 | (A_05 ^ B_05) & CIN_05; endmodule
(3) Behavioural
module FA_behavioural( input
A_05, B_05, CIN_05, output
reg SUM, CARRY); always
@(A_05, B_05, CIN_05) begin
SUM = A_05 ^ B_05 ^ CIN_05;
CARRY = A_05 & B_05 | (A_05 ^ B_05) & C_05; end
endmodule
Schematic
Simulation:
1 . Functional Verification
A_05
B_05
y_ 05_i
x_05_i
z_05_i
Cin_05EC – 403 | VD
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2 . Post Synthesis
3 . Post Implementation
4 . Power
A_05
A_05_IBUF
CIN_05_IBUF
CIN_05
B _05
B _05_IBUF
A_05
A_05_IBUF
B _05
B _05_IBU
F
CIN_05_IBUF
CIN_05EC – 403 | VD
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5. Utilization
Conclusion:
On performing this practical, we observed schematic of full adder as well as
behavioural simulation, post synthesis,
post implementation waveforms respectively. Moreover, we also observed its power
output and time utilization.
CIN_05
B _05
