Nouf Ali Alshamsi
201601184
→indef
→ depend on O
→ indep
→ depend on l & 2
→ indep
→ indep
O
→ depends on
→ depends on 3
→ indep on
depends 3
→
→ depends on 2
SUB
Instruction fetch Decode execute write back
0 ADD Rs IR , I R2 O l 2 3
Load Rbi [ Rs] I 4
92
I 2
Rt IRS 13 5
63
AND 2 3
ADD RiiR6IR7 3 4 10 It
SRL Rtl Ro 18 4 5 6
75
4
OR Rz , R4iR7 5 6 8 10
6 SUB Rsi Rsi R4 6 7 9 12
7- ADD Ro , Rallo 7 8 12 13
g LOAD RGICRS] 8 9 13 18
q SUB R2 IR , 1R6 9 10 19 20
10 AND R3iR > 115 10 11 14 15
RAW :
I Iz) ft , Iz) (I , ( Iss 14 )
, → ,
→ , →
Ivy s
WAR :(Iz → I3 )
WAW : II , → Iz) i ( Iu Is )
RAW :O
.
100
RI ←
read
RAW write then read
[Link]#:::::e::::e::i
'
:
[Link]#u c-
:
⇐
Iz -
Ils
-
WDR
Iz -
568
Ig → Iz
Is
Beats
-
-53
-
gu
RAW ( J2 → E3 ) C -13 Iu) CI4 Is) ( I2→I4 ) b Ii Ria 100
IU 9 -_
I
: → i . :
-
. , → ,
z
- In
Iz RIB Rza
WAR : CI , → Iy) i CI , → Is) , ( Iz → Iy ) , (Iz →Is ) Iz : = t Rya
Ju -
IS
WAW : CI, → Iz) ,
CI , → Is) , (J2 → Is ) I3 : Rzb =
Rya - 25
154 : Ry b -
-
Ric tR39
Is : Rid =Rict30 .
a . [ can ) +
(I - 2) X1 ] u b .
n > 16 MIPS Rate -
- Cna -
2 + DX
Can -
att ) X x=4 40=1162 - 21-174
40=[1521-1] 4
36-60
=
6×01 → 11=0.6
:
'
÷÷÷÷÷÷⇐
:
a. n = 9 Speedups nd -
Lt) b . n=7 speedup -
na -
att
& = F- O -
25 9 Co 257
-
-
O -
251-1 =3 117710.25) -
0251--1=5
(O 25 ) ( 17 )
O' 25×9=0.75 75% 85%
'
y =
-
=
go =
-
= 0,85 =
3 5
# of cycles CN)
a . L2 N clock cycles b '
loop ,
-
section ( M)
ly 1 clock cycle Total - 2L t
IC Ktp )
26 N clock cycles
a .
2N t) clock cycles
ti :
MAR
←
CIR address) 8D z I
tz : MBR ← memory A -
B B= 010 I
tz : MBR ← complement CMBR) At C- B) B 's 1010
A
l t
tu : MBR ← increment ( MBR)
ts : Ri ← crit CMBR) Bmf O N tf
a. Time required =
propagation time of the bust copy time .
40+15=55 NS
135 NS Z ← pct I
b .
40+801-15 =
pc ← 2-
a. ti :
Y ← CIR address) b , t , : MAR ← IR ( address) c ,
ti : MAR ← CIR address)
Ez : 2- CAC )tCY ) tz M BR tz: MBR
← :
← memory ← memory
£3 AC CZ )
:
← tz :
y ←
(MBR) ts : MAR ← ( MBR)
ty : 2- ← CAC) t Cy ) tu : MBR ← memory
ts : AC ← 2- ts : y ← MBR
to : 2- ← ( Adt (Y )
£7 : Ac ←
CZ )
a.
poping b .
push
ti : Sp ← Spt ) ti : SP ← Csp ) -
l
MBR ← ( Rs)
£2 : MAR ← CSP)
£3 :
memory ← ( MBR)
a .
The flag represent boolean variable that are input to the control unit logic together with the time input and other flag , they determine control unit output .
b. The phase of the instruction cycle is implicit the organization of the microprogram . certain in the microprogram memory correspond to each of the four phases .
-
ta .
2
"
=
16 x -
-
4 bits address selection field : 2×-16 X=4 bits
b .
32 -
is -
4=13 bits address field ! 32-4-15=13 bits
c .
213×32=262744 Control memory : 213 X 32
Two of the code in the address selection field must be dedicated to the purpose .
Example : ooo could correspond to no branch .
Ill in it to unconditional branch .
2X 1024 to bits for control
= x -
memory
The map opcode : Xx XXX
mapping = xxx x x ooo when 8 bit control is used
control address -
- Oo xxxxx ooo to bits control with 2ms B bits with o .
26 -
1=63 24 -
I = IS
25 -
1=31 23 -
1=7
22 -
I =3
to bit : * 6 bits micro -
operation
20 - I so
* 4 bits micro -
operation
number of action -
-
2b -
1=63
n u
n = 24 - 1=15
total number of actions : 631-15=78
