Digital System Design

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Content

• Logic gates
• Multiplexers
• Demultiplexer
• Decoder
• Encoder
• Binary Adders
• Subtractor
• Combinational circuit designing
Apply Your Knowledge
1. Decimal 43 in hexadecimal and BCD number system is respectively……. and ……..
2. For the gate in the given figure the output will be ……….

3. P is a 8-bit signed integer. The 2's complement representation of P is (F8)hexa. The 2's
complement representation of 8*P
4. For the truth table of the given figure Y = ………….
Designing logic circuits from Statement

Three pressure sensors each produce a logic 0 output when the

pressure at their location falls below a pre-set pressure, P1, P2 or P3.
A pump is to be turned ON whenever the pressure at all three
locations falls below the pre-set value. Obtain the Boolean equation
describing the required circuit.

P1’.P2’.P3’
Designing logic circuits from Statement

A temperature sensor T1, produces a logic 0v, when the

temperature at its location is greater than 25°C. Another temp
sensor T2 produces logic 1v when the temp at its location is above
10°C. A heater H is to be turned ON when the temp is between 10
and 25°C. If the temp falls below 10°C, an alarm is to be sounded.
Obtain the Boolean equation for the required circuit.
Heater= T1.T2
Alarm= T2’
Boolean Properties
Commutative: a+b=b+a a•b=b•a
Associative: a + (b + c) = (a + b) + c a • (b • c) = (a • b) • c
Identity: a+0=a a•1=a
Distributive a + (b • c) = (a + b) • (a + c) a • (b + c) = (a • b) + (a • c)
Complementary: a + a' = 1 a • a' = 0
Involution : (a' ) ' = a
Uniting: X • Y + X • Y' = X (X + Y) • (X + Y') = X
Absorption: X+X•Y=X X • (X + Y) = X
(X + Y') • Y = X • Y (X • Y') + Y = X + Y
Concensus:
(X • Y) + (Y • Z) + (X' • Z) = X • Y + X' • Z (X + Y) • (Y + Z) • (X' + Z) = (X + Y) • (X' + Z)
de Morgan's Theorem:

X Y X' Y' (X + Y)‘ X' • Y'

(X + Y)' = X' • Y' 0 0 1 1 1 1
NOR is equivalent to AND 0 1 1 0 0 0
1 0 0 1 0 0
with inputs complemented 1 1 0 0 0 0

X Y X' Y' (X • Y)‘ X' + Y'

(X • Y)' = X' + Y' 0 0 1 1 1 1
NAND is equivalent to OR 0 1 1 0 1 1
with inputs complemented 1 0 0 1 1 1
1 1 0 0 0 0
Logic gates

X Y
NOT X' 𝑋 ~X X Y 0 1
1 0

X Y Z
X 0 0 0
AND X•Y XY XY Y Z 0 1 0
1 0 0
1 1 1

X X Y Z
OR X+Y XY Z 0 0 0
Y 0 1 1
1 0 1
1 1 1
Logic gates
NAND X Y Z
X 0 0 1
Z 0 1 1
Y
1 0 1
1 1 0

NOR X Y Z
X 0 0 1
Z 0 1 0
Y 1 0 0
1 1 0

XOR X Y X
X
0
Y
0
Z
0 X xor Y = X Y' + X' Y
Z
Y 0 1 1 X or Y but not both
1 0 1 ("inequality", "difference")
1 1 0
XNOR X = Y X Y Z X xnor Y = X Y + X' Y'
X 0 0 1
Z 0 1 0
X and Y are the same
Y
1 0 0 ("equality", "coincidence")
1 1 1
From Boolean expressions to logic gates

• More than one way to map expressions to gates

 e.g., Z = A' • B' • (C + D) = (A' • (B' • (C + D)))

use of 3-input gate

A Z A
B T1 B Z
C T2 C
D D
Venn diagram representation

A.B A+B

A’.B A xor B
NANDs are special!
The NAND gate is universal: it can replace all other gates!
 NOT x’ = (xx)’ [ because xx = x ]

 AND

xy = ((xy)’)’ [ Inversion law]

 OR
x+y
= (x’ y’)’ [ xx = x, and yy = y ]
= ((xx)’ (yy)’)’ [ DeMorgan’s law ]
Making NAND circuits
• The easiest way to make a NAND circuit is to start with a regular,
primitive gate-based diagram.
• Two-level circuits are trivial to convert, so here is a slightly more
complex random example.
Converting to a NAND circuit
• Step 1: Convert all AND gates to NAND gates using AND-NOT symbols, and convert
all OR gates to NAND gates using NOT-OR symbols.
Converting to NAND, concluded
• Step 2: Make sure you added bubbles along lines in pairs ((x’)’ = x). If not, then
either add inverters or complement the input variables.
NOR gates

• The NOR operation is the dual of the NAND.

• NOR gates are also universal.
• We can convert arbitrary circuits to NOR diagrams by following a procedure
similar to the one just shown:
 Step 1:
 Convert all OR gates to NOR gates (OR-NOT), and all AND gates to NOR gates (NOT-
AND).
 Step 2:
 Make sure that you added bubbles along lines in pairs. If not, then either add inverters
or complement input variables.
Converting to a NOR circuit
Implementation of Boolean Functions

Technology independent
 Canonical forms
 Two-level forms
 Multi-level forms

Technology choices
 Packages of a few gates
 Regular logic
 Two-level programmable logic
 Multi-level programmable logic
Canonical Form of Boolean Expressions

• Truth table is the unique signature of a Boolean function

• Many alternative gate realizations may have the same truth table
• Canonical forms
 Standard forms for a Boolean expression
 Provides a unique algebraic signature
Sum-of-products canonical forms
Also known as disjunctive normal form
Also known as minterm expansion
F = 001 011 101 110 111
F = A'B'C + A'BC + AB'C + ABC' + ABC

A B C F F'
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 0 F' = A'B'C' + A'BC' + AB'C'
 Sum-of-products canonical form (cont’d)
Product term (or minterm)
 ANDed product of literals – input combination for which output is true
 Each variable appears exactly once, in true or inverted form (but not both)
A B C minterms F in canonical form:
0 0 0 A'B'C' m0 F(A, B, C) = m(1,3,5,6,7)
0 0 1 A'B'C m1 = m1 + m3 + m5 + m6 + m7
0 1 0 A'BC' m2 = A'B'C + A'BC + AB'C + ABC' + ABC
0 1 1 A'BC m3
1 0 0 AB'C' m4 canonical form  minimal form
1 0 1 AB'C m5 F(A, B, C) = A'B'C + A'BC + AB'C + ABC + ABC'
1 1 0 ABC' m6 = (A'B' + A'B + AB' + AB)C + ABC'
1 1 1 ABC m7 = ((A' + A)(B' + B))C + ABC'
= C + ABC'
short-hand notation for = ABC' + C
minterms of 3 variables = AB + C
Product-of-sums canonical form
Also known as conjunctive normal form
Also known as maxterm expansion

F= 000 010 100

F= (A + B + C) (A + B' + C) (A' + B + C)

A B C F F'
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 0

F' = (A + B + C') (A + B' + C') (A' + B + C') (A' + B' + C) (A' + B' + C')
Product-of-sums canonical form (cont’d)
• Sum term (or maxterm)
 ORed sum of literals – input combination for which output is false
 each variable appears exactly once, in true or inverted form (but not both)
A B C maxterms F in canonical form:
0 0 0 A+B+C M0 F(A, B, C) = M(0,2,4)
0 0 1 A+B+C' M1 = M0 • M2 • M4
0 1 0 A+B'+C M2 = (A + B + C) (A + B' + C) (A' + B + C)
0 1 1 A+B'+C' M3
1 0 0 A'+B+C M4 canonical form  minimal form
1 0 1 A'+B+C' M5 F(A, B, C) = (A + B + C) (A + B' + C) (A' + B + C)
1 1 0 A'+B'+C M6
= (A + B + C) (A + B' + C) (A + B + C) (A' + B + C)
1 1 1 A'+B'+C' M7
= (A + C) (B + C)

short-hand notation for

maxterms of 3 variables
Four alternative two-level implementations of F = AB + C
A F(A, B, C) = A'B'C + A'BC + AB'C + ABC' + ABC
= AB + C
B canonical sum-of-products
F1

minimized sum-of-products
F2 F(A, B, C) = (A + B + C) (A + B' + C) (A' + B + C)
= (A + C) (B + C)
canonical product-of-sums
F3

minimized product-of-sums
F4
Karnaugh maps
Flat map of Boolean cube
 Wrap–around at edges
 Hard to draw and visualize for more than 4 dimensions
 Virtually impossible for more than 6 dimensions
Alternative to truth-tables to help visualize adjacencies
 Guide to applying the uniting theorem
 On-set elements with only one variable changing value are adjacent unlike the
situation in a linear truth-table A B F
A 0 0 1
B 0 1
0 1 1 0 1 0
0 2
1 0 1
1 0 0
1 3 1 1 0
Karnaugh maps (cont’d)
Numbering scheme based on Gray–code
 e.g., 00, 01, 11, 10
 Only a single bit changes in code for adjacent map cells

AB A
C 00 01 11 10
A
0
0 2 6 4
0 4 12 8
C 1
1 3 7 5
1 5 13 9 D
B
A 3 7 15 11
C
0 2 6 4 2 6 14 10
B
C 13 = 1101= ABC’D
1 3 7 5
B
Adjacencies in Karnaugh maps

Wrap from first to last column

Wrap top row to bottom row

011 111
A
110
000 010 110 100 010

B 001
C 001 011 111 101 C 101
B 100
000 A
Karnaugh map examples
F=
A
1 1
Cout = B’
B 0 0

f(A,B,C) = m(0,4,6,7)
A
0 0 1 0 AB + ACin + BCin

Cin 0 1 1 1
A B
1 0 0 1
obtain the
C 0 0 1 1
complement
B AC + B’C’ + AB’
of the function
by covering 0s
with subcubes
More Karnaugh map examples
A
0 0 1 1
G(A,B,C) = A
C 0 0 1 1
B

A
1 0 0 1
F(A,B,C) = m(0,4,5,7) = AC + B’C’
C 0 0 1 1
B

A
F' simply replace 1's with 0's and vice versa
0 1 1 0
F'(A,B,C) =  m(1,2,3,6) = BC’ + A’C
C 1 1 0 0
B
Karnaugh map: 4-variable example
F(A,B,C,D) = m(0,2,3,5,6,7,8,10,11,14,15)

F=
C + A’BD + B’D’

A 1111
0111
1 0 0 1

0 1 0 0
D
Y
1 1 1 1 Z
W
C 1000
1 1 1 1 0000 X
B

find the smallest number of the largest possible

subcubes to cover the ON-set
(fewer terms with fewer inputs per term)
Karnaugh maps: don’t cares

f(A,B,C,D) = m(1,3,5,7,9) + d(6,12,13)

f = A’D + B’C’D

A
0 0 X 0

1 1 X 1
D
1 1 0 0
C
0 X 0 0
B
Karnaugh maps: don’t cares (cont’d)
f(A,B,C,D) = m(1,3,5,7,9) + d(6,12,13)
 f = A'D + B'C'D without don't cares
 f= with don't cares
A'D + C'D

A
by using don't care as a "1"
0 0 X 0
a 2-cube can be formed
1 1 X 1
rather than a 1-cube to cover
D this node
1 1 0 0
C don't cares can be treated as
0 X 0 0 1s or 0s
B depending on which is more
advantageous
 Multiplexer

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Multiplexer (MUX)
• A MUX is a digital switch that has multiple Multiplexer
inputs (sources) and a single output Block Diagram
(destination).
• The select lines determine which input is
connected to the output. 2N 1

MUX
Inputs Output
• MUX Types (sources) (destination)

 2-to-1 (1 select line)

 4-to-1 (2 select lines) N
 8-to-1 (3 select lines)
 16-to-1 (4 select lines) Select
Lines
Typical Application of a MUX
Multiple Sources Selector Single Destination

MP3 Player
Docking Station

D0
Laptop
D1

MUX
Sound Card Y
D2

D3

Surround Sound System

Digital B A Selected Source

Satellite
0 0 MP3
0 1 Laptop
1 0 Satellite
Digital
1 1 Cable TV
Cable TV
2-to-1 Multiplexer (MUX)

S Y

0 I0

1 I1
4-to-1 Multiplexer (MUX)

D0

MUX
D1
Y
D2

D3

B A

B A Y

0 0 D0

0 1 D1

1 0 D2

1 1 D3
8-to-1 Multiplexer

SEL2 SEL1 SEL0 Y

0 0 0 IN0 Y = SEL2’. SEL1’. SEL0’ . IN0 +

0 0 1 IN1 SEL2’. SEL1’. SEL0 . IN1 +
SEL2’. SEL1. SEL0’ . IN2 +
0 1 0 IN2
SEL2’. SEL1. SEL0 . IN3 +
0 1 1 IN3
SEL2. SEL1’. SEL0’ . IN4 +
1 0 0 IN4 SEL2. SEL1’. SEL0 . IN5 +
1 0 1 IN5 SEL2. SEL1. SEL0’ . IN6 +
SEL2. SEL1. SEL0 . IN7
1 1 0 IN6

1 1 1 IN7
Mux as a Universal Gate
 Implement XOR, NAND gate using 2:1 mux

A B
(Select (input XOR NAND B D0 XOR 1 D0 NAND
line) line)
B’ D1 B’ D1
0 0 0 1
B 1
0 1 1 1 s s
A A
1 0 1 1
B’ B’
1 1 0 0
Implement S and CN of full adder multiplexers.
The figure below shows a multiplexer where s1 and s0 are the select lines.
I0 to I3 are the input datalines, EN is the enable line, and F(P,Q,R) is the
output. F is ___

Option a
A four-variable Boolean function is realized using 4 1 multiplexers as shown in the
figure

Option C
The minimized expression for F( U, V, W, X)
Consider the circuit shown in the figure

Option B
The Boolean expression F implemented by the circuit
 Demultiplexer

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What is a Demultiplexer (DEMUX)?

• A DEMUX is a digital switch with a single Demultiplexer

input (source) and a multiple outputs Block Diagram
(destinations).
• The select lines determine which output

DEMUX
the input is connected to. 1 2N
Input Outputs
(source) (destinations)
• DEMUX Types
 1-to-2 (1 select line)
 1-to-4 (2 select lines) N
 1-to-8 (3 select lines) Select
 1-to-16 (4 select lines) Lines 46
Typical Application of a DEMUX
Single Source Selector Multiple Destinations

B/W Laser
Printer

Fax
Machine

D0

DEMUX
X D1

D2 Color Inkjet
Printer
D3

B A Selected Destination
0 0 B/W Laser Printer Pen
0 1 Fax Machine Plotter

1 0 Color Inkjet Printer

1 1 Pen Plotter

47
1-to-2 De-Multiplexer (DEMUX)

S D0 D1

0 I 0

1 0 I
1-to-4 De-Multiplexer (DEMUX)
D0

DEMUX
D1
X
D2

D3

B A

B A D0 D1 D2 D3

0 0 X 0 0 0

0 1 0 X 0 0

1 0 0 0 X 0

1 1 0 0 0 X
 Decoder

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What is a decoder
• In older days, the (good) printers used be like typewriters:
 To print “A”, a wheel turned, brought the “A” key up, which then was struck on the
paper.
• Letters are encoded as 8 bit codes inside the computer.
 When the particular combination of bits that encodes “A” is detected, we want to
activate the output line corresponding to A
 (Not actually how the wheels worked)
• How to do this “detection” : decoder
• General idea: given a k bit input,
 Detect which of the 2^k combinations is represented
 Produce 2^k outputs, only one of which is “1”.

51
What a decoder does
• A n-to-2n decoder takes an n-bitn input and produces 2n outputs. The n inputs represent a binary number
that determines which of the 2 outputs is uniquely true.
• A 2-to-4 decoder operates according to the following truth table.
 The 2-bit input is called S1S0, and the four outputs are Q0-Q3.
 If the input is the binary number i, then output Qi is uniquely true.
S1 S0 Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
• For instance, if the input S1 S0 = 10 (decimal 2), then output Q2 is true, and Q0, Q1, Q3 are all false.
• This circuit “decodes” a binary number into a “one-of-four” code.

52
How can you build a 2-to-4 decoder?
• Follow the design procedures from last time! We have a truth table, so we can write
equations for each of the four outputs (Q0-Q3), based on the two inputs (S0-S1).

S1 S0 Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

• In this case there’s not much to be simplified. Here are the equations:
Q0 = S1’ S0’
Q1 = S1’ S0
Q2 = S1 S0’
Q3 = S1 S0

53
A picture of a 2-to-4 decoder

S1 S0 Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

54
Enable inputs
• Many devices have an additional enable input, which is used to “activate” or
“deactivate” the device.
• For a decoder,
 EN=1 activates the decoder, so it behaves as specified earlier. Exactly one of the outputs will be
1.
 EN=0 “deactivates” the decoder. By convention, that means all of the decoder’s outputs are 0.
• We can include this additional input in the decoder’s truth table:
EN S1 S0 Q0 Q1 Q2 Q3
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

55
 An aside: abbreviated truth tables
EN S1 S0 Q0 Q1 Q2 Q3
• In this table, note that whenever EN=0,
0 0 0 0 0 0 0
the outputs are always 0, regardless of 0 0 1 0 0 0 0
inputs S1 and S0. 0 1 0 0 0 0 0
0 1 1 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

• We can abbreviate the table by writing x’s EN S1 S0 Q0 Q1 Q2 Q3

in the input columns for S1 and S0. 0 x x 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

56
 A 3-to-8 decoder
• Larger decoders are similar. Here is a 3-to-8 decoder.
 The block symbol is on the right.
 A truth table (without EN) is below.
 Output equations are at the bottom right.
• Again, only one output is true for any input combination.

S2 S1 S0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0 0 0 1 0 0 0 0 0 0 0 Q0 = S2’ S1’ S0’
0 0 1 0 1 0 0 0 0 0 0 Q1 = S2’ S1’ S0
0 1 0 0 0 1 0 0 0 0 0 Q2 = S2’ S1 S0’
0 1 1 0 0 0 1 0 0 0 0 Q3 = S2’ S1 S0
1 0 0 0 0 0 0 1 0 0 0 Q4 = S2 S1’ S0’
1 0 1 0 0 0 0 0 1 0 0 Q5 = S2 S1’ S0
1 1 0 0 0 0 0 0 0 1 0 Q6 = S2 S1 S0’
1 1 1 0 0 0 0 0 0 0 1 Q7 = S2 S1 S0

57
So what good is a decoder?
• Do the truth table and equations look familiar?

S1 S0 Q0 Q1 Q2 Q3
0 0 1 0 0 0 Q0 = S1’ S0’
0 1 0 1 0 0 Q1 = S1’ S0
1 0 0 0 1 0 Q2 = S1 S0’
1 1 0 0 0 1 Q3 = S1 S0
• Decoders are sometimes called minterm generators.
 For each of the input combinations, exactly one output is true.
 Each output equation contains all of the input variables.
 These properties hold for all sizes of decoders.
• This means that you can implement arbitrary functions with decoders. If you have a sum of
minterms equation for a function, you can easily use a decoder (a minterm generator) to implement
that function.

58
Design example: addition

• Let’s make a circuit that adds three 1-bit inputs X, Y and Z.

• We will need two bits to represent the total; let’s call them C and S, for “carry” and
“sum.” Note that C and S are two separate functions of the same inputs X, Y and Z.
• Here are a truth table and sum-of-minterms equations for C and S.
X Y Z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
C(X,Y,Z) = m(3,5,6,7)
0 + 1 + 1 = 10 0 1 1 1 0
S(X,Y,Z) = m(1,2,4,7)
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1 1 + 1 + 1 = 11

59
Using just one decoder
• Since the two functions C and S both have the same inputs, we could
use just one decoder instead of two.

C(X,Y,Z) = m(3,5,6,7)
S(X,Y,Z) = m(1,2,4,7)

60
Encoder
Encoder
• Symbol to coded format conversion

• one-hot to binary converter

Example: 4 to 2 Encoder

i3 i2 i1 i0 Valid y1 Y0
i3 i2 i1 i0 y1 Y0 0 0 0 0 0 X X
0 0 0 1 0 0 0 0 0 1 1 0 0
0 0 1 0 0 1 0 0 1 0 1 0 1
0 1 0 0 1 0 0 1 0 0 1 1 0
1 0 0 0 1 1 1 0 0 0 1 1 1
8 to 3 Encoder
O7 O6 O5 O4 O3 O2 O1 O0 Y2 Y1 Y0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1
8 to 3 Encoder
O7 O6 O5 O4 O3 O2 O1 O0 Valid Y2 Y1 Y0

0 0 0 0 0 0 0 0 0 X X X

0 0 0 0 0 0 0 1 1 0 0 0

0 0 0 0 0 0 1 0 1 0 0 1

0 0 0 0 0 1 0 0 1 0 1 0

0 0 0 0 1 0 0 0 1 0 1 1

0 0 0 1 0 0 0 0 1 1 0 0

0 0 1 0 0 0 0 0 1 1 0 1

0 1 0 0 0 0 0 0 1 1 1 0

1 0 0 0 0 0 0 0 1 1 1 1
Decimal to BCD Convertor
Decimal B3 B2 B1 B0
D0 0 0 0 0
D1 0 0 0 1
D2 0 0 1 0
D3 0 0 1 1
D4 0 1 0 0
D5 0 1 0 1
D6 0 1 1 0
D7 0 1 1 1
D8 1 0 0 0
D9 1 0 0 1
Decimal to BCD Convertor Decimal B3 B2 B1 B0 Valid
D0 0 0 0 0 1
D1 0 0 0 1 1
D2 0 0 1 0 1
D3 0 0 1 1 1
D4 0 1 0 0 1
D5 0 1 0 1 1
D6 0 1 1 0 1
D7 0 1 1 1 1
D8 1 0 0 0 1
D9 1 0 0 1 1
D10 1 0 1 0 0
D11 1 0 1 1 0
D12 1 1 0 0 0
D13 1 1 0 1 0
D14 1 1 1 0 0
D15 1 1 1 1 0
Priority Encoder
4 to 2 Priority Encoder
i3 i2 i1 i0 Valid y1 Y0

0 0 0 0 0 X X

0 0 0 1 1 0 0

0 0 1 X 1 0 1

0 1 X X 1 1 0

1 X X X 1 1 1
 Binary Adders

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Half Adder
Half Adder using NAND Logic
Full Adder
Input Output
A B Cin S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Full Adder using Half adder
Input Output
C = Ʃm(3,5,6,7)
A B Cin S C
= A’ B Cin + A B’ Cin + A B Cin’ +AB Cin
0 0 0 0 0
=( A’ B+ A B’) Cin + AB (Cin’ + Cin )
0 0 1 1 0 =(A xor B) Cin + AB
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Ripple Carry Adder
Carry Look-ahead Adder
Output
Input

A B Cin C
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Carry Look-ahead Adder
Half Subtractor
Half Subtractor
Design example 1: Comparing 2-bit numbers

• Let’s design a circuit that compares two 2-bit numbers, A and B. The
circuit should have three outputs:
 G (“Greater”) should be 1 only when A > B.
 E (“Equal”) should be 1 only when A = B.
 L (“Lesser”) should be 1 only when A < B.
• Make sure you understand the problem.
 Inputs A and B will be 00, 01, 10, or 11 (0, 1, 2 or 3 in decimal).
 For any inputs A and B, exactly one of the three outputs will be 1.
Step 1: How many inputs and outputs?
• Two 2-bit numbers means a total of four inputs.
 We should name each of them.
 Let’s say the first number consists of digits A1 and A0 from left to right, and the second number is B1
and B0.
• The problem specifies three outputs: G, E and L.

• Here is a block diagram that shows the inputs and outputs explicitly.
• Now we just have to design the circuitry that goes into the box.
 Step 2: Functional specification
• For this problem, it’s probably easiest to start A1 A0 B1 B0 G E L
with a truth table. This way, we can explicitly 0 0 0 0
show the relationship (>, =, <) between inputs. 0 0 0 1
0 0 1 0
• A four-input function has a sixteen-row truth 0 0 1 1
table. 0 1 0 0
0 1 0 1
• It’s usually clearest to put the truth table rows in 0 1 1 0 0 0 1
binary numeric order; in this case, from 0000 to 0 1 1 1
1111 for A1, A0, B1 and B0. 1 0 0 0
1 0 0 1
• Example: 01 < 10, so the sixth row of the truth 1 0 1 0
table (corresponding to inputs A=01 and B=10) 1 0 1 1
shows that output L=1, while G and E are both 0. 1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
 Step 2: Functional specification
• For this problem, it’s probably easiest to start A1 A0 B1 B0 G E L
with a truth table. This way, we can explicitly 0 0 0 0 0 1 0
show the relationship (>, =, <) between inputs. 0 0 0 1 0 0 1
0 0 1 0 0 0 1
• A four-input function has a sixteen-row truth 0 0 1 1 0 0 1
table. 0 1 0 0 1 0 0
0 1 0 1 0 1 0
• It’s usually clearest to put the truth table rows in 0 1 1 0 0 0 1
binary numeric order; in this case, from 0000 to 0 1 1 1 0 0 1
1111 for A1, A0, B1 and B0. 1 0 0 0 1 0 0
1 0 0 1 1 0 0
• Example: 01 < 10, so the sixth row of the truth 1 0 1 0 0 1 0
table (corresponding to inputs A=01 and B=10) 1 0 1 1 0 0 1
shows that output L=1, while G and E are both 0. 1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
Step 3: Simplified Boolean expressions

Let’s use K-maps. There are three functions (each with the same inputs A1 A0 B1 B0), so we
need three K-maps.
B1 B1 B1
0 0 0 0 1 0 0 0 0 1 1 1
1 0 0 0 0 1 0 0 0 0 1 1
A0 A0 A0
1 1 0 1 0 0 1 0 0 0 0 0
A1 A1 A1
1 1 0 0 0 0 0 1 0 0 1 0
B0 B0 B0

G(A1,A0,B1,B0) = E(A1,A0,B1,B0) = L(A1,A0,B1,B0) =

A1 A0 B0’ + A1’ A0’ B1’ B0’ + A1’ A0’ B0 +
A0 B1’ B0’ + A1’ A0 B1’ B0 + A0’ B1 B0 +
A1 B1’ A1 A0 B1 B0 + A1’ B1
A1 A0’ B1 B0’
Step 4: Drawing the circuits
G = A1 A0 B0’ + A0 B1’ B0’ + A1 B1’
E = A1’ A0’ B1’ B0’ + A1’ A0 B1’ B0 + A1 A0 B1 B0 + A1 A0’ B1 B0’
L = A1’ A0’ B0 + A0’ B1 B0 + A1’ B1

LogicWorks has gates with

NOTs attached (small
bubbles) for clearer
diagrams.
Design example 1.2: Binary BCD
Binary to BCD Converter B1 B2 B3 B4 A B C D E
B3 0000 0 0 0 0 0
0 0 0 0 A= 0001 0 0 0 0 1
0 0 0 0 0010 0 0 0 1 0
B2
0011 0 0 0 1 1
1 1 1 1
B1 0100 0 0 1 0 0
0 0 1 1
0101 0 0 1 0 1
B4
0110 0 0 1 1 0
B3
0111 0 0 1 1 1
0 0 0 0 B=
1000 0 1 0 0 0
0 0 0 0 1001 0 1 0 0 1
B2
0 0 0 0 1010 1 0 0 0 0
B1
1 1 0 0
1011 1 0 0 0 1
B4 1100 1 0 0 1 0
1101 1 0 0 1 1
1110 1 0 1 0 0
1111 1 0 1 0 1
Design example 1.2: Binary BCD
Binary to BCD Converter B1 B2 B3 B4 A B C D E
B3 0000 0 0 0 0 0
0 0 0 0 C= 0001 0 0 0 0 1
1 1 1 1 0010 0 0 0 1 0
B2
0011 0 0 0 1 1
0 0 1 1
B1 0100 0 0 1 0 0
0 0 0 0
0101 0 0 1 0 1
B4
0110 0 0 1 1 0
B3
0111 0 0 1 1 1
0 0 1 1 D=
1000 0 1 0 0 0
0 0 1 1 1001 0 1 0 0 1
B2
1 1 0 0 1010 1 0 0 0 0
B1
0 0 0 0
1011 1 0 0 0 1
B4 1100 1 0 0 1 0
1101 1 0 0 1 1
1110 1 0 1 0 0
1111 1 0 1 0 1
Design example 1.2: Binary BCD
Binary to BCD Converter B1 B2 B3 B4 A B C D E
B3 0000 0 0 0 0 0
0 1 1 0 E= 0001 0 0 0 0 1
0 1 1 0 0010 0 0 0 1 0
B2
0011 0 0 0 1 1
0 1 1 0
B1 0100 0 0 1 0 0
0 1 1 0
0101 0 0 1 0 1
B4
0110 0 0 1 1 0
0111 0 0 1 1 1
1000 0 1 0 0 0
1001 0 1 0 0 1
1010 1 0 0 0 0
1011 1 0 0 0 1
1100 1 0 0 1 0
1101 1 0 0 1 1
1110 1 0 1 0 0
1111 1 0 1 0 1
Design example 2: 2x2-bit multiplier
A2 A1 B2 B1 P8 P4 P2 P1
0 0 0 0 0 0 0 0
0 1 0 0 0 0
1 0 0 0 0 0
1 1 0 0 0 0
A1 P1 0 1 0 0 0 0 0 0
A2 P2 0 1 0 0 0 1
1 0 0 0 1 0
B1 P4 1 1 0 0 1 1
B2 P8 1 0 0 0 0 0 0 0
0 1 0 0 1 0
1 0 0 1 0 0
1 1 0 1 1 0
1 1 0 0 0 0 0 0
block diagram 0 1 0 0 1 1
and 1 0 0 1 1 0
truth table 1 1 1 0 0 1

4-variable K-map
for each of the 4
output functions
Design example 2: 2x2-bit multiplier (cont’d)
A2 A2
K-map for P8 K-map for P4
0 0 0 0 0 0 0 0
P4 = A2B2B1'
0 0 0 0 0 0 0 0
B1 + A2A1'B2 B1
0 0 1 0 0 0 0 1
B2 P8 = A2A1B2B1 B2
0 0 0 0 0 0 1 1
A1 A1

A2 A2
0 0 0 0
K-map for P2 K-map for P1 0 0 0 0
P1 = A1B1
0 0 1 1 0 1 1 0
B1 B1
0 1 0 1 0 1 1 0
B2 P2 = A2'A1B2 B2
0 1 1 0 + A1B2B1' 0 0 0 0
A1 + A2B2'B1 A1
+ A2A1'B1
Incrementer and Decrementer
Design example 3: BCD increment by 1
I8 I4 I2 I1 O8 O4 O2 O1
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0
I1 O1 0 1 0 0 0 1 0 1
0 1 0 1 0 1 1 0
I2 O2 0 1 1 0 0 1 1 1
I4 O4 0 1 1 1 1 0 0 0
1 0 0 0 1 0 0 1
I8 O8 1 0 0 1 0 0 0 0
1 0 1 0 X X X X
1 0 1 1 X X X X
1 1 0 0 X X X X
1 1 0 1 X X X X
block diagram 1 1 1 0 X X X X
and 1 1 1 1 X X X X
truth table
4-variable K-map for each of
the 4 output functions
 Design example 3: BCD increment by 1 (cont’d)
I8 I8
O8 O4
0 0 X 1 0 1 X 0

0 0 X 0 0 1 X 0
I1 I1
0 1 X X O8 = I4 I2 I1 + I8 I1' 1 0 X X
I2 O4 = I4 I2' + I4 I1' + I4’ I2 I1 I2
0 0 X X 0 1 X X
I4 O2 = I8’ I2’ I1 + I2 I1' I4

I8
O1 = I1' I8
O2 O1
0 0 X 0 1 1 X 1

1 1 X 0 0 0 X 0
I1 I1
0 0 X X 0 0 X X
I2 I2
1 1 X X 1 1 X X
I4 I4
Thank You