23EC3ESHDL HDL Programming

Question Bank for CIE 1

Unit I
VLSI Design flow:
1. Show the typical design flow for VLSI IC and explain all the blocks. [Jun’19] 07
2. With a neat block diagram, explain the typical VLSI IC design flow. [Jun’18, Aug’18] 06, 08
3. Show the typical design flow for VLSI IC and explain all the blocks. Also recall the different
levels of abstraction in Verilog. [Jul’17] 07
4. Explain the design flow of VLSI IC circuits. [Jul’24] 10
Verilog HDL:
5. Explain the Verilog data types with syntax. [Jun’16] 06
6. Explain the Verilog data types with syntax and example. [May’23] 07
7. Discuss the various data types used in Verilog HDL. [Aug’23, May’17] 07, 06
8. Explain the different types of modeling in Verilog. [Jul’16] 07
Design Methodologies:
9. Design 4-bit ripple carry adder using top-down design methodology with stimulus. [Jun’18] 10
10. Apply the concept of top-down design methodology to develop a 4-bit ripple carry counter using
Verilog. [Jun’17] 08
11. Model the Verilog code for D flipflop with asynchronous active low input (reset). [Jul’17] 05
12. Design a 4-bit T flip-flop based Ripple- Carry counter using top-down design methodology. Also
write the test bench to generate clock and reset inputs. [Apr’24] 11
13. Briefly describe the bottom-up design methodology taking the example of a full adder to be de-
signed using only 2-input NAND gates as the leaf cells. (Verilog code is not required.) 10
14. Illustrate the bottom-up design methodology by realizing an 8-to-1 multiplexer using 2-to-1 mul-
tiplexers as building blocks. 10
Components of Simulation:
15. Illustrate the components of simulation using 4-bit ripple carry adder as an example. [Jul’17] 08
16. Differentiate between the following: [Aug’18] 06
(a) Register and wire data types
(b) $monitor and $display system tasks
(c) $finish and $stop
17. Discuss the difference between monitor and display statements with example. [Apr’24] 04

1
Modules and Ports:

18. What is a module? What are the basic components of a module? Explain with an example.
[Aug’18] 06

19. Explain the components of a Verilog module with neat diagram. [Jul’24] 10

20. Explain the port connections rules followed in Verilog HDL programming. [May’23] 06

21. List the various components of a Verilog module. [Jun’18] 04

22. Discuss the rules to be followed while connecting the Verilog ports with an example code.
[Jul’19] 06

23. Explain how ports are connected to external signals in Verilog description with an example pro-
gram definition. [Jun’18] 10

24. Discuss the rules to be followed while connecting the Verilog ports with an example code.
[Apr’24] 05

Unit II
Gate-level Modeling:

24. Design a 2-to-1 multiplexer using bufif0 and bufif1 gates as shown below. The delay specification
for gates b1 and b2 are as follows. Write the verilog code and apply stimulus to test the output
values. [Jun’16] 10

25. Develop a Verilog gate level model for the 4X1 Multiplexer using its gate structure. [Apr’24] 04

26. Design a 4 to 1 multiplexer with block diagram, truth table, logic diagram and Verilog gate level
description. [Jul’24] 10

27. Design and implement 16:1 multiplexer using 4:1 multiplexer using Verilog. [Jun’17] 06

28. Design and implement 16:1 Multiplexer using two 8:1 MUX in Verilog HDL. [Jul’16] 08

29. Implement the 4×1 MUX using Verilog gate-level modeling. Also write the testbench. [Jul’19] 08

30. Write the Verilog gate level implementation of S-R flip flop. [May’16] 06

31. Develop a positive edge triggered D flip-flop using Verilog gate level Implementation. Also write
the test bench to test the code. [May’16] 08

32. Design and implement a full adder using Verilog HDL in the following design methodologies:

2
 (a) Gate-level modeling
(b) Using two half-adders [Jul’16] 06

33. Implement the Verilog gate level description for the positive edge triggered D flip-flop. Also write
test bench. [May’18] 10

34. Design and implement the 2-to-4 decoder using gate-level description. Also write the simulation
block. [Jun’17] 06

35. Apply the concept of module instantiations in Verilog for a full subtractor using 2 half subtractors.
Use gate-level modeling for half subtractors. [Jul’17] 07

36. Using gate-level description style, write a Verilog HDL model for the following logic circuit shown
in Figure 1. Apply stimulus to test the output values. [Jun’19] 08

Figure 1: Question 36

37. Explain the Verilog gate primitives of inverter and buffer with symbol and truth table. [May’18] 04

Gate Delays:

38. Briefly describe gate delays. [Aug’18] 05

39. Deduce the design block for the given Verilog code and draw the waveforms for the stimulus given:
module example(out, a, b, c); [Jul’17] 05
input a, b, c;
output out;
and #5 a1(e, a, b);
or #4 a2(out, e, c);
endmodule
module stimulus;
reg A, B, C;
wire OUT;
example ex1(OUT, A, B, C);
initial
begin
A = 1’b0, B = 1’b0, C = 1’b0;
#10 A = 1’b1, B = 1’b1, C = 1’b1;
#10 A = 1’b1, B = 1’b0, C = 1’b0;
#20 $finish;
end
endmodule

40. Write the Verilog code and analyze effect of given gate delays with waveform for the module given
below in Figure 2. Write the test bench. [May’18] 06

3
 a
#5
b
#4 out
c

Figure 2: Question 40

41. Deduce the design block for the given Verilog code and draw the waveforms for the stimulus given:
module sr latch(q, qbar, s, r, ck); 10
output q, qbar;
input s, r, ck;
wire sbar, rbar;
nand #5 U0 (sbar, s, ck);
nand #5 U1 (rbar, r, ck);
nand #5 U2 (q, sbar, qbar);
nand #5 U3 (qbar, rbar, q);
endmodule
module stimulus;
reg s, r, ck=1’b0;
wire q, qbar;
sr latch uut (q, qbar, s, r, ck);
always #10 ck = ∼ck;
initial
begin
s = 1’b1; r = 1’b0;
#25 s = 1’b0; r = 1’b0;
#20 s = 1’b1; r = 1’b1;
#20 s = 1’b0; r = 1’b1;
#20 $finish;
end
endmodule