Iterative Combinational Circuits

 Arithmetic functions
• Operate on binary vectors
• Use the same subfunction in each bit position
 Can design functional block for sub-function and
repeat to obtain functional block for overall
function
 Cell – sub-function block
 Iterative array - an array of interconnected cells
 An iterative array can be in a single dimension (1D)
or multiple dimensions (wavefront and systolic
array)
Block Diagram of a 1D Iterative Array

 Example: n = 32
• Number of inputs = ?
• Truth table rows = ?
• Equations with huge number of terms
 Iterative array takes advantage of the regularity
to make design feasible
Functional Blocks: Addition

 Addition Development:
• Half-Adder (HA), a 2-input bit-wise addition functional
block,
• Full-Adder (FA), a 3-input bit-wise addition functional
block,
• Ripple Carry Adder, an iterative array to perform binary
addition
• Carry-Look-Ahead Adder (CLA), a hierarchical
structure to improve performance.
Functional Block: Half-Adder

 A 2-input, 1-bit width binary adder that performs the

following computations:
X 0 0 1 1
+ Y + 0 + 1 + 0 + 1
C S 0 0 0 1 0 1 1 0
 A half adder adds two bits to produce a two-bit sum
 The sum is expressed as a sum bit , S and a carry bit, C

X Y C S
0 0 0 0
 The half adder can be specified a truth
0 1 0 1
table for S and C 
1 0 0 1
1 1 1 0
Logic Simplification: Half-Adder
S Y C Y
 The K-Map for S, C is:
0 11 0 1

X 12 3 X 2 13
 This is a pretty trivial map! By inspection:
S= X  Y + X  Y = X  Y
S = (X + Y )  (X + Y )
 and
C = XY
C = (( X Y ) )
 These equations lead to several implementations.
Five Implementations: Half-Adder

 We can derive following sets of equations for a

half-adder:
(a ) S = X  Y + X  Y (d ) S = ( X + Y )  C
C = XY C = (X + Y )
( b ) S = ( X + Y )  ( X + Y ) ( e) S = X  Y
C = X Y C = X Y
(c) S = (C + X  Y )
C = X Y
 (a), (b), and (e) are SOP, POS, and XOR
implementations for S.
 In (c), the C function is used as a term in the
AND-NOR implementation of S, and in (d), the C
function is used in a POS term for S.
Implementations: Half-Adder

 The most common half

adder implementation is: X
Y S
(e)
S= X  Y C
C = XY

 A NAND only implementation is:

C
S = (X + Y )  C X
C = (( X Y ) )
S
Y
 Functional Block: Full-Adder

 A full adder is similar to a half adder, but includes

a carry-in bit from lower stages. Like the half-
adder, it computes a sum bit, S and a carry bit, C.
• For a carry-in (Z) of 0, Z 0 0 0 0
X 0 0 1 1
it is the same as the
+ Y + 0 + 1 + 0 + 1
half-adder:
C S 00 0 1 0 1 1 0

Z 1 1 1 1
• For a carry-in (Z) of 1: X 0 0 1 1
+ Y + 0 + 1 + 0 + 1
C S 0 1 1 0 1 0 11
Logic Optimization: Full-Adder

 Full-Adder Truth Table: X Y Z C S

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
 Full-Adder K-Map: 1 1 0 1 0
1 1 1 1 1

S Y C Y
1 1 1
0 1 3 2 0 1 3 2

X 1 1 X 1 1 1
4 5 7 6 4 5 7 6

Z Z
Equations: Full-Adder

 From the K-Map, we get:

S= XY Z+ XY Z+ XY Z+ XY Z
C = X Y + X Z + Y Z = X Y + (X + Y) Z
 The S function is the three-bit XOR function (Odd
Function):
S= X  Y  Z
 The Carry bit C is 1 if both X and Y are 1 (the sum is 2), or if
the sum is 1 and a carry-in (Z) occurs. Thus C can be re-
written as:

C = X Y + (X  Y ) Z
 The term X·Y is carry generate.
 The term XY is carry propagate.
 Implementation: Full Adder

 Full Adder Schematic Ai Bi

Gi
 Here X, Y, and Z, and C
(from the previous pages)
are A, B, Ci and Co,
respectively. Also,
G = generate and Pi
P = propagate. Ci

 Note: This is really a combination

of a 3-bit odd function (for S) and
Carry logic (for Co): Ci+1 Si
(G = Generate) OR (P =Propagate AND Ci = Carry In)
Ci+1 = G + P · Ci
Sequential Adder

 1-bit memory and 2 4-bit memory

 Only one full-adder!
 4 clocks to get the output
 The 1-bit memory defines the circuit state (0 or 1)
 Binary Adders

 To add multiple operands, we “bundle” logical

signals together into vectors and use functional
blocks that operate on the vectors
 Example: 4-bit ripple carry Description Subscript Name
3210
adder: Adds input vectors
Carry In 0110 Ci
A(3:0) and B(3:0) to get
a sum vector S(3:0) Augend 1011 Ai
Addend 0011 Bi
 Note: carry out of cell i
Sum 1110 Si
becomes carry in of cell
i+1 Carry out 0011 Ci+1
4-bit Ripple-Carry Binary Adder

 A four-bit Ripple Carry Adder made from

four 1-bit Full Adders:
B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1
FA FA FA FA C0

C4 S3 S2 S1 S0

74LS283
 Ripple-Carry Adders (cont’d)

 Critical delay
• The propagation of carry from low to high order stages
• 1111 + 0001 is the worst case addition
• Carry must propagate through all bits

S0, C1 Valid S1, C2 Valid S2, C3 Valid S3, C4 Valid

Ai Bi
Gi
C0
S0
C1
S1
Pi
Ci C2
S2
C3
S3
Ci+1
Si C4
T0 T2 T4 T6 T8
 Ripple-Carry Adders

 Critical Delay
• The propagation of carry from low to high order stages

Cin
4 stage adder
0 A 1 N+1
0 B A0 S0 2
N Cin B0 C1 2
Cout
0 A N+2
B A1
0 1 S1 3
B1 C2 4
late arriving two gate delays
signal to compute Cout A2 S2 5
B2 C3 6

A3 S3 7
B3 Cout 8
 Ai Bi
Ripple-Carry Adders (cont’d) Gi

Pi
Ci

Ci+1 Si
Carry-Lookahead Logic

 Carry generate: Gi = Ai Bi
• Must generate carry when A = B = 1
 Carry propagate: Pi = Ai xor Bi

 Sum and Cout can be re-expressed in terms of

generate/propagate: Ai B i
• Si = Ai xor Bi xor Ci
Gi
= Pi xor Ci

• Ci+1 = Gi + Ci Pi Pi
Ci

Ci+1 Si
 Carry-Lookahead Logic (cont’d)

 Re-express the carry logic as follows:

• C1 = G0 + P0C0
• C2 = G1 + P1C1 = G1 + P1G0 + P1P0C0
• C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0
• C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

 Each of the carry equations can be implemented with

two-level logic
• All inputs are now directly derived from data inputs and not
from intermediate carries
• this allows computation of all sum outputs to proceed in
parallel
Carry-Lookahead Implementation (cont’d)

Ai B i
Gi

Pi
Ci

Ci+1 Si
 2’s Complement Adder/Subtractor

 Subtraction can be done by addition of the 2's Complement.

1. Complement each bit (1's Complement.)
2. Add 1 to the result.
 The circuit shown computes A + B and A – B:
 For S = 1, subtract, B 3 A B 3A B2 A B2 A 1 1 0 0

the 2’s complement A–B =A+(–B)=A+B'+1

of B is formed by using S

XORs to form the 1’s

comp and adding the 1
applied to C0.
 For S = 0, add, B is FA
C
FA
C
3
FA
C
FA
2 C 1 0

passed through
unchanged
C4 S3 S2 S1 S0
Carry-Select Adder

 Redundant hardware to make carry calculation go faster

• Compute two high-order sums in parallel while waiting for carry-in
• One assuming carry-in is 0 and another assuming carry-in is 1
• Select correct result once carry-in is finally computed

C8 4-bit adder 1 adder

[7:4]
high

C8 4-bit adder 0
[7:4] adder
low

five 1 0 1 0 1 0 1 0 1 0 C4 4-Bit Adder C0

2:1 mux [3:0]

C8 S7 S6 S5 S4 S3 S2 S1 S0
 Carry-Lookahead Adder
with Cascaded Carry-Lookahead Logic

 Carry-lookahead adder
• 4 four-bit adders with internal carry lookahead
• Second level carry lookahead unit extends lookahead to 16 bits

4 4 4 4 4 4 4 4

A[15-12] B[15-12] A[11-8] B[11-8] A[7-4] B[7-4] A[3-0] B[3-0]

C12 C8 C4 C0
4-bit Adder 4-bit Adder 4-bit Adder 4-bit Adder @0
P G P G P G P G
4 4 4 4

S[15-12] S[11-8] S[7-4] S[3-0]

@8 @2 @3 @8 @2 @3 @7 @2 @3 @4 @2 @3
@5 @5 @4

P3 G3 C3 P2 G2 C2 P1 G1 C1 P0 G0
C16 C4 C0 C0
@4 Lookahead Carry Unit @0
P3-0 G3-0
@3 @5
Overflow Detection

 Overflow occurs if n + 1 bits are required to contain the

result from an n-bit addition or subtraction
 Overflow can occur for:
• Addition of two operands with the same sign
• Subtraction of operands with different signs
 Signed number overflow cases with correct result sign
0 0 1 1
+ 0 -1 - 0 + 1
0 0 1 1
 Detection can be performed by examining the result signs
which should match the signs of the top operand
Overflow Detection

 The simplest way to implement overflow is V = Cn + Cn - 1

where Cn and Cn-1 are the carries in 2’s complement
respectively from e to the sign bit:
• Cn = 0 and Cn-1 = 1 means An = Bn = 0 and Sn = 1
• Cn = 1 and Cn-1 = 0 means An = Bn = 1 and Sn = 0
Other Arithmetic Functions

 Convenient to design the functional blocks by

contraction - removal of redundancy from circuit
to which input fixing has been applied
 Functions
• Incrementing
• Decrementing
• Multiplication by Constant
• Division by Constant
• Zero Fill and Extension
Design by Contraction

 Contraction is a technique for simplifying the logic

in a functional block to implement a different
function
 The new function must be realizable from the
original function by applying rudimentary functions
to its inputs
• Contraction is treated here only for application of 0s and
1s (not for X and X)
• After application of 0s and 1s, equations or the logic
diagram are simplified.
Design by Contraction Example: Incrementer

 Contraction of a ripple carry adder to incrementer for n = 3

• Set B = 001
X 0
X 0
X

counting up

• The middle cell can be repeated to make an incrementer with n > 3.

 Decrementer D=A-110; D=A+11 1112

Ai 1
Gi counting down Ai A0

Ai Ci+1 Ci C1
Ci 0

Ci+1
Si Si S0
An Ai A0

Cn Ci+1 Ci C1

Sn Si S0
Multiplication/Division by 2n

 (a) Multiplication B3 B2 B1 B0
by 1002
• Shift left by 2
0 0
 (b) Division
by 1002 C5 C4 C3 C2 C1 C0
(a)
• Shift right by 2
• Remainder
preserved B3 B2 B1 B0

0 0
C3 C2 C1 C0 C2 1 C2 2
(b)
 Multiplication by a Constant

 Multiplication of B(3:0) by 101

Comparator

 Used to implement comparison operators (=, )

Equal or
Different?