University of Bahri
Collage of Applied and Industrial Science
Department of Electronics and Instrumentation
Assignment 1:
Name: Ahmed Mohamed Shogar Adam
8086 Architecture and pin description:
o Intel 8086 microprocessor is the enhanced version of Intel
8085 microprocessor. It was designed by Intel in 1976.
o The 8086 microprocessor is a16-bit, N-channel, HMOS
microprocessor. Where the HMOS is used for "High-speed
Metal Oxide Semiconductor".
o Intel 8086 is built on a single semiconductor chip and
packaged in a 40-pin IC package. The type of package is DIP
(Dual Inline Package).
o Intel 8086 uses 20 address lines and 16 data- lines. It can
directly address up to 220 = 1 Mbyte of memory.
o It consists of a powerful instruction set, which provides
operation like division and multiplication very quickly.
o 8086 is designed to operate in two modes, i.e., Minimum
and Maximum mode.
8086 Microprocessor chips:
The pins discerption as follow: -
AD0-AD15 (Address Data Bus): Bidirectional address/data lines. These are low order
address bus. They are multiplexed with data.
When these lines are used to transmit memory address, the symbol A is used instead
of AD, for example, A0- A15.
A16 - A19 (Output): High order address lines. These are multiplexed with status
signals.
A16/S3, A17/S4: A16 and A17 are multiplexed with segment identifier signals S3 and
S4.
A18/S5: A18 is multiplexed with interrupt status S5.
A19/S6: A19 is multiplexed with status signal S6.
BHE/S7 (Output): Bus High Enable/Status. During T1, it is low. It enables the data
onto the most significant half of data bus, D8-D15. 8-bit device connected to upper
half of the data bus use BHE signal. It is multiplexed with status signal S7. S7 signal is
available during T3 and T4.
RD (Read): For read operation. It is an output signal. It is active when LOW.
Ready (Input): The addressed memory or I/O sends acknowledgment through this
pin. When HIGH, it denotes that the peripheral is ready to transfer data.
RESET (Input): System reset. The signal is active HIGH.
CLK (input): Clock 5, 8 or 10 MHz.
INTR: Interrupt Request.
NMI (Input): Non-maskable interrupt request.
TEST (Input): Wait for test control. When LOW the microprocessor continues
execution otherwise waits.
VCC: Power supply +5V dc.
GND: Ground.
# 8085 instruction set:
An instruction of a computer is a command given to the computer to perform a
specified operation on given data. In microprocessor, the instruction set is the
collection of the instructions that the microprocessor is designed to execute.
The programmer writes a program in assembly language using these instructions.
These instructions have been classified into the following groups:
Instruction Set Explanation States Flags Addre- Machine Example
ssing Cycles
MOV r1, r2 Move the content 4 none Register 1 MOV A, B
[r1] ← [r2] of the one register
to another
MOV r, M Move the content 7 none Register 2 MOV B, M
[r]←[[H-L]] of memory to Indirect
register
MOV M, r Move the content 7 none Register 2 MOV M, C
[[H-L]]←[r] of register to Indirect
memory
MVI r, data Move immediate 7 None Immediate 3 MVI M, 08
[r] ←data data to register Register
LXI rp, data 16 Load Register pair 10 None Immediate 3 LXI H,
[rp] ←data 16 bits, immediate 2500H
[rh] ←8 MSBs, [rl]
←8 LSBs of data
LDA addr Load Accumulator 13 None Direct 4 LDA 2400
[A] ←[addr] direct H
STA Addr Store accumulator 13 None Direct 4 STA 2000H
[addr] ←[A] direct
LHLD addr Load H-L pair direct 16 None Direct 5 LHLD
[L] ←[addr], [H] ← 2500H
[addr + 1 ]
SHLD addr Store H-L pair direct 16 None Direct 5 SHLD 2500
[addr] ←[L], [addr H
+1] ← [H]
LDAX rp Load accumulator 7 None Register 2 LDAX B
[A] ←[[rp]] indirect Indirect
STAX rp Store accumulator 7 None Register 2 STAX D
[[rp]] ←[A] indirect Indirect
XCHG Change the 4 None Register 1
[H-L] ↔[D-E] contents of H-L with
D-E pair
# set instructions for 8086:
Instruction Description
MOV Moves data from register to register, register to memory, memory to register, memory
to accumulator, accumulator to memory, etc.
LDS Loads a word from the specified memory locations into specified register. It also loads a
word from the next two memory locations into DS register.
LES Loads a word from the specified memory locations into the specified register. It also
loads a word from next two memory locations into ES register.
LEA Loads offset address into the specified register.
LAHF Loads low order 8-bits of the flag register into AH register.
SAHF Stores the content of AH register into low order bits of the flags register.
XLAT/XLATB Reads a byte from the lookup table.
XCHG Exchanges the contents of the 16-bit or 8-bit specified register with the contents of AX
register, specified register or memory locations.
PUSH Pushes (sends, writes or moves) the content of a specified register or memory location(s)
onto the top of the stack.
POP Pops (reads) two bytes from the top of the stack and keeps them in a specified register,
or memory location(s).
POPF Pops (reads) two bytes from the top of the stack and keeps them in the flag register.
IN Transfers data from a port to the accumulator or AX, DX or AL register.
OUT Transfers data from accumulator or AL or AX register to an I/O port identified by the
second byte of the instruction.
