Chapter 8.
Pipelining
Overview
Pipelining
is widely used in modern
processors.
Pipelining improves system performance in
terms of throughput.
Pipelined organization requires sophisticated
compilation techniques.
Basic Concepts
Making the Execution of
Programs Faster
Use
faster circuit technology to build the
processor and the main memory.
Arrange the hardware so that more than one
operation can be performed at the same time.
In the latter way, the number of operations
performed per second is increased even
though the elapsed time needed to perform
any one operation is not changed.
Traditional Pipeline Concept
Laundry
Example
Ann, Brian, Cathy, Dave
each have one load of clothes
to wash, dry, and fold
Washer takes 30 minutes
Dryer
takes 40 minutes
Folder
takes 20 minutes
Traditional Pipeline Concept
6 PM
10
Midnight
11
Time
30
40
20 30
40
20 30
40
20 30
Sequential
A
B
C
D
40
20
laundry takes 6 hours
for 4 loads
If they learned pipelining, how
long would laundry take?
Traditional Pipeline Concept
6 PM
T
a
s
k
O
r
d
e
r
10
11
Midnight
Time
30
40
40
40
40 20
A
Pipelined
B
C
D
laundry takes
3.5 hours for 4 loads
Traditional Pipeline Concept
6 PM
Pipelining
9
Time
T
a
s
k
O
r
d
e
r
30
A
B
C
D
40
40
40
40
20
doesnt help latency
of single task, it helps
throughput of entire workload
Pipeline rate limited by slowest
pipeline stage
Multiple tasks operating
simultaneously using different
resources
Potential speedup = Number
pipe stages
Unbalanced lengths of pipe
stages reduces speedup
Time to fill pipeline and time
to drain it reduces speedup
Stall for Dependences
Use the Idea of Pipelining in a
Computer
Fetch + Execution
I1
I2
Time
I3
Clockcycle
F
I2
Interstagebuffer
B1
Instruction
fetch
unit
I3
Execution
unit
(b)Hardwareorganization
F1
E1
Instruction
I1
(a)Sequentialexecution
Time
F2
E2
F3
E3
(c)Pipelinedexecution
Figure8.1.Basicideaofinstructionpipelining.
Use the Idea of Pipelining in a
Computer
Time
Clockcycle
F1
D1
E1
W1
F2
D2
E2
W2
F3
D3
E3
W3
F4
D4
E4
Instruction
Fetch + Decode
+ Execution + Write
I1
I2
I3
I4
W4
(a)Instructionexecutiondividedintofoursteps
Interstagebuffers
D:Decode
instruction
andfetch
operands
F:Fetch
instruction
B1
E:Execute
operation
B2
(b)Hardwareorganization
Textbook page: 457
Figure8.2. A4stagepipeline.
W:Write
results
B3
Role of Cache Memory
Each pipeline stage is expected to complete in one
clock cycle.
The clock period should be long enough to let the
slowest pipeline stage to complete.
Faster stages can only wait for the slowest one to
complete.
Since main memory is very slow compared to the
execution, if each instruction needs to be fetched
from main memory, pipeline is almost useless.
Fortunately, we have cache.
Pipeline Performance
The
potential increase in performance
resulting from pipelining is proportional to the
number of pipeline stages.
However, this increase would be achieved
only if all pipeline stages require the same
time to complete, and there is no interruption
throughout program execution.
Unfortunately, this is not true.
Pipeline Performance
Time
Clockcycle
F1
D1
E1
W1
F2
D2
Instruction
I1
I2
I3
I4
I5
F3
E2
W2
D3
E3
W3
F4
D4
E4
W4
F5
D5
E5
Figure8.3. Effectofanexecutionoperationtakingmorethanoneclockcycle.
Pipeline Performance
The previous pipeline is said to have been stalled for two clock
cycles.
Any condition that causes a pipeline to stall is called a hazard.
Data hazard any condition in which either the source or the
destination operands of an instruction are not available at the
time expected in the pipeline. So some operation has to be
delayed, and the pipeline stalls.
Instruction (control) hazard a delay in the availability of an
instruction causes the pipeline to stall.
Structural hazard the situation when two instructions require
the use of a given hardware resource at the same time.
Pipeline Performance
Time
Instruction
hazard
Clockcycle
F1
D1
E1
W1
D2
E2
W2
F3
D3
E3
Instruction
I1
I2
F2
I3
W3
(a)Instructionexecutionstepsinsuccessiveclockcycles
Time
Clockcycle
F1
F2
F2
F2
F2
F3
D1
idle
idle
idle
D2
D3
E1
idle
idle
idle
E2
E3
W1
idle
idle
idle
W2
Stage
F:Fetch
D:Decode
E:Execute
W:Write
Idle periods
stalls (bubbles)
W3
(b)Functionperformedbyeachprocessorstageinsuccessiveclockcycles
Figure8.4. PipelinestallcausedbyacachemissinF2.
Pipeline Performance
Structural
hazard
Load X(R1), R2
Time
Clockcycle
F1
D1
E1
W1
F2
D2
F3
E2
M2
W2
D3
E3
W3
F4
D4
E4
Instruction
I1
I2 (Load)
I3
I4
I5
F5
D5
Figure8.5. EffectofaLoadinstructiononpipelinetiming.
Pipeline Performance
Again, pipelining does not result in individual
instructions being executed faster; rather, it is the
throughput that increases.
Throughput is measured by the rate at which
instruction execution is completed.
Pipeline stall causes degradation in pipeline
performance.
We need to identify all hazards that may cause the
pipeline to stall and to find ways to minimize their
impact.
Quiz
Four
instructions, the I2 takes two clock
cycles for execution. Pls draw the figure for 4stage pipeline, and figure out the total cycles
needed for the four instructions to complete.
Data Hazards
Data Hazards
We must ensure that the results obtained when instructions are
executed in a pipelined processor are identical to those obtained
when the same instructions are executed sequentially.
Hazard occurs
A3+A
B4A
No hazard
A5C
B 20 + C
When two operations depend on each other, they must be
executed sequentially in the correct order.
Another example:
Mul R2, R3, R4
Add R5, R4, R6
Data Hazards
Time
Clockcycle
F1
D1
E1
W1
F2
D2
D2A
E2
W2
D3
E3
W3
F4
D4
E4
Instruction
I1 (Mul)
I2 (Add)
I3
I4
F3
W4
Figure8.6. PipelinestalledbydatadependencybetweenD2andW1.
Figure 8.6. Pipeline stalled by data dependency between D2 and W1.
Operand Forwarding
Instead
of from the register file, the second
instruction can get data directly from the
output of ALU after the previous instruction is
completed.
A special arrangement needs to be made to
forward the output of ALU to the input of
ALU.
Source1
Source2
SRC1
SRC2
Register
file
ALU
RSLT
Destination
(a)Datapath
SRC1,SRC2
RSLT
E:Execute
(ALU)
W:Write
(Registerfile)
Forwardingpath
(b)Positionofthesourceandresultregistersintheprocessorpipeline
Figure8.7. Operandforw ardinginapipelinedprocessor.
Handling Data Hazards in
Software
Let
the compiler detect and handle the
hazard:
I1: Mul R2, R3, R4
NOP
NOP
I2: Add R5, R4, R6
The compiler can reorder the instructions to
perform some useful work during the NOP
slots.
Side Effects
The previous example is explicit and easily detected.
Sometimes an instruction changes the contents of a register
other than the one named as the destination.
When a location other than one explicitly named in an instruction
as a destination operand is affected, the instruction is said to
have a side effect. (Example?)
Example: conditional code flags:
Add R1, R3
AddWithCarry R2, R4
Instructions designed for execution on pipelined hardware should
have few side effects.
Instruction Hazards
Overview
Whenever
the stream of instructions supplied
by the instruction fetch unit is interrupted, the
pipeline stalls.
Cache miss
Branch
Unconditional Branches
Time
Clockcycle
F1
E1
Instruction
I1
I2 (Branch)
I3
Ik
Ik+1
F2
Executionunitidle
E2
F3
Fk
Ek
Fk+1
Ek+1
Figure8.8. Anidlecyclecausedbyabranchinstruction.
Time
Branch Timing
Clockcycle
I1
F1
D1
E1
W1
F2
D2
E2
F3
D3
F4
I2 (Branch)
I3
- Branch penalty
- Reducing the penalty
I4
Fk
Ik
Ik+1
Dk
Ek
Wk
Fk+1
Dk+1
E k+1
(a)BranchaddresscomputedinEx ecutestage
Time
Clockcycle
I1
F1
D1
E1
W1
F2
D2
I2 (Branch)
I3
Ik
Ik+1
F3
Dk
Ek
Wk
X
Fk
Fk+1
D k+1 E k+1
(b)BranchaddresscomputedinDecodestage
Figure8.9. Branchtiming.
Instruction Queue and
Prefetching
Instructionfetchunit
Instructionqueue
F:Fetch
instruction
D:Dispatch/
Decode
unit
E:Execute
instruction
W:Write
results
Figure8.10.UseofaninstructionqueueinthehardwareorganizationofFigure8.2b.
Conditional Braches
A
conditional branch instruction introduces the
added hazard caused by the dependency of
the branch condition on the result of a
preceding instruction.
The decision to branch cannot be made until
the execution of that instruction has been
completed.
Branch instructions represent about 20% of
the dynamic instruction count of most
programs.
