ECE 485/585

Microprocessor System Design

Yuchen Huang

Maseeh College of Engineering

and Computer Science

Initial content copied verbatim from ECE 485/585 material

developed by Professor Mark G. Faust @ PSU ECE
Serial Buses
- Part 1
 Serial Buses
• Bus Trends
• Clocking
• Line Codes
• Differential Signaling
• USB 2.0, USB 3.0

ECE 485/585: Serial Buses 3

 Bus Trends

• Parallel to Serial
• Lower Voltage
– Can’t accomplish large voltage swings at high speed
– Power consumption
• Differential Signaling
• Clock Forwarding and Clock Embedding
• Encoding
– Line codes: NRZI
– 8b/10b, “bit-stuffing”

ECE 485/585: Serial Buses 4

 Why Serial?
“Parallel” “Serial”

+
-
Device A Device B Device A +
Device B
-

10 bidirectional wires at 250Mbps pair unidirectional wires at 2500Mbps (2.5Gbps)

ECE 485/585: Serial Buses 5

 Traditional Parallel Bus

Device A Device B

• Used in low to medium 100 MHz range

• Issues
– Board trace length mismatch effect on skew
– Clock skew across devices
– Faster data rate squeezes “eye”

ECE 485/585: Serial Buses 6

 Source Synchronous Bus

Device A Device B

• Used in 200MHz to 1.6GHz range

• Clock signal is “forwarded” with data
• Design impact:
– Board layout track length mismatch
still adds to skew
– Eliminates skew error term caused by clock
domain skew
– Allows faster cycle times than parallel
ECE 485/585: Serial Buses 7
 Source Synchronous - Clock Forward
Clock

Data 1
Data 2
Data 3
Data 4

• Clock is transmitted continuously from Tx to Rx

• Removes clock distribution skew
• Examples
– HyperTransport
– Parallel RapidIO
ECE 485/585: Serial Buses 8
 Source Synchronous - Latch Forward
Latch
Data 1
Data 2
Data 3
Data 4

• Latch assertion is transmitted when valid data is present

• Examples
– Bi-directional buses
– Memory Interfacing (e.g. DDR)

ECE 485/585: Serial Buses 9

 Embedded Clock
Data
Clock

Clock signal embedded with data

• Clock signal is embedded with data

– Edge density guaranteed by encoding scheme
• Examples
– PCI Express
– USB
– Serial RapidIO
– Infiniband
ECE 485/585: Serial Buses 10
 SerDes (Serial/Deserializer)

Tx
Serialize

10 x 250Mbps 1 x 2.5Gbps
• Low Speed • High Speed
• Parallel Data • Serial Data

Deserialize
Rx

ECE 485/585: Serial Buses 11

 SerDes - Parallel and Serial Conversion

Register
10-bit TxP
Serializer
Parallel Interface TxN

SysClk XmitClk
Register

Rx Parallel Clock Recovery RxP

Interface and
10-bit Data Deserializer RxN

Recovered Clock

Differential signals (a pair of signals) are used to increase noise immunity.

Differential signals: only when the two signals go the opposite direction, it signals a transition.
ECE 485/585: Serial Buses 12
 Differential Signal Increases Noise Immunity

This is NOT a transition since the two signals didn’t go

opposite direction.

Differential signals (a pair of signals) are used to increase noise immunity.

Differential signals: only when the two signals go the opposite direction, it signals a transition.

ECE 485/585: Serial Buses 13

 Edge Lock Technique (Tracking Receiver)
Device Device
A B
Device A sends pulse train to Device B

Device B “locks” onto edges

to be in sync with pulse stream

ECE 485/585: Serial Buses 14

 Ensuring Edge Density: m-of-n codes
• Some 8-bit code words have too few 1s (or 0s) to ensure edge density
sufficient to recover clock
• 8b10 encoding (developed by IBM in 1983)
– Use subset of 210 10-bit code words having a “balanced” number of 0s and 1s
– Benefits
• Ensure edge density
• Avoid DC bias at receiver from imbalance
– Running disparity for unbalanced codewords

– 256 data characters 8 bit byte 10 bit code

• All 8-bit bytes
• 12 control characters (INIT, etc)
Table lookup
Device A Device B
+
Parallel 8B/10B 8B/10B Parallel
TX FIFO Serializer _
Deserializer RX FIFO
Data Encoder Decoder Data

Parallel 8B/10B + 8B/10B Parallel

RX FIFO Deserializer _ Serializer TX FIFO
Data Decoder Encoder Data

ECE 485/585: Serial Buses 15

 8b/10b Transmission Code
Name Hex Value 8-bit binary 10-bit
Encode
D0.0 00 00000000 1001110100
D1.0 01 00000001 0111010100
D2.0 10 00000010 1011010100
D3.0 11 00000011 1100011011

• Reasons for using 8B/10B encoding/decoding

• Guarantees transition density to ensure correct PLL operation
• Error correction to detect signaling errors
• Ensures signal is DC balanced – no DC offset develops over time
• Support of special characters that can be used as delimiters for control, such as sync
or framing, or other generalized commands

ECE 485/585: Serial Buses 16

 Codes for Serial Data Transmission
• Objectives/Properties of Line Codes
• Facilitate clock recovery by providing edge density
• Avoid DC bias by being DC balanced
• NRZ – Non Return to Zero • Noise immunity if used with differential pairs
• NRZI – Non Return to Zero Invert (on ones)
– Transition (edge) based code
– Differential signaling: USB
• RZ – Return to Zero
• BPRZ – Bipolar Return to Zero
– “DC balanced”
– MLT-3 (100 Base T Ethernet)
• Manchester encoding
– Guarantees transition every bit cell
– Facilitates clock recovery
– Requires higher bandwidth
– Original coax-based 10 Mbps Ethernet
• Other techniques for DC balancing (and edge density)
– m-out-of-n-codes (e.g. 8B10B): Gigbabit Ethernet

ECE 485/585: Serial Buses 17

 NRZI Encoding
• Ensures data integrity
– Better than NRZ in transition-based communication
• Edge-based rather than level-based (LVDS)
– Edge density for PLL (phase locked loop)
• Clock extraction
• 0 toggles data output level
• 1 holds data output level
• “Bit stuffing” (alternative to 8b/10b encoding)
– after six consecutive 1s a 0 is inserted in the data stream
– discarded by receiver
– “Bit stuffing” is used in USB 2.0 to ensure edge density to facilitate
identifying bit frames.

ECE 485/585: Serial Buses 18

 Differential Signaling
• Differential, point to point
– Complementary signals transmitted
– Receiver detects voltage difference between lines
– Low amplitudes (200mV - 400mV typical), high speeds
– Good noise immunity
• Pair routed together – noise cancels out
• LVDS – Low Voltage Differential Signaling
– ANSI/TIA/EIA 644-1995 standard (signaling only, not protocol or connectors)
– 3.125 Gbps, +/- 350mV
– “Gbps at mWs” -- High speed & low power consumption
– FibreChannel, Gigabit Ethernet, HDMI, DVI

May be edge-based!

ECE 485/585: Serial Buses 19