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Lecture - 03
Basic concepts and system buses (cont’d.)
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Basic Instruction Cycle
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Fetch Cycle
At the beginning of each instruction cycle the processor fetches an
instruction from memory
The program counter (PC) holds the address of the instruction to be
fetched next
The processor increments the PC after each instruction fetch so that
it will fetch the next instruction in sequence
The fetched instruction is loaded into the instruction register (IR)
The processor interprets the instruction and performs the required
action
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Action Categories
• Data transferred from • Data transferred to or from
processor to memory or a peripheral device by
from memory to processor transferring between the
processor and an I/O
module
Processor- Processor-
memory I/O
Data
Control
processing
• An instruction may specify • The processor may
that the sequence of perform some arithmetic
execution be altered or logic operation on data
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Example
of
Program
Execution
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Instruction Cycle State Diagram
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Classes of Interrupts
Program Generated by some conditions that occurs as a result of an instruction
execution, such as arithmetic overflow, division by zero, attempt to
execute an illegal machine instruction, and reference outside a user’s
allowed memory space
Timer Generated by a timer within the processor. This allows the operating
system to perform certain functions on a regular basis
I/O Generated by an I/O controller, to signal normal completion of an
operation or to signal a variety of error conditions
Hardware failure Generated by a failure, such as power failure or memory parity error
Program Flow Control 9
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Transfer of Control via Interrupts
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Instruction Cycle With Interrupts
Instruction Cycle State Diagram
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With Interrupts
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Transfer of
Control
Multiple
Interrupts
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+ Time Sequence of 14
Multiple Interrupts Example
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I/O Function
I/O module can exchange data directly with the processor
Processor can read data from or write data to an I/O module
Processor identifies a specific device that is controlled by a particular I/O
module
I/O instructions rather than memory referencing instructions
In some cases it is desirable to allow I/O exchanges to occur directly
with memory
The processor grants to an I/O module the authority to read from or write
to memory so that the I/O memory transfer can occur without tying up the
processor
The I/O module issues read or write commands to memory relieving the
processor of responsibility for the exchange
This operation is known as direct memory access (DMA)
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Computer
Modules
The interconnection structure must support the following 17
types of transfers:
I/O to or
Memory to Processor I/O to Processor
from
processor to memory processor to I/O
memory
An I/O
module is
allowed to
exchange
Processor Processor
Processor Processor data directly
reads an reads data
writes a unit sends data to with memory
instruction or from an I/O
of data to the I/O without going
a unit of data device via an
memory device through the
from memory I/O module
processor
using direct
memory
access
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A communication pathway Signals transmitted by any one
connecting two or more devices device are available for reception B u s
• Key characteristic is that it is a shared by all other devices attached to
transmission medium the bus I n t e
• If two devices transmit during the same r c o n
time period their signals will overlap n e c t
and become garbled i o n
Typically consists of multiple
communication lines Computer systems contain a
• Each line is capable of transmitting number of different buses that
signals representing binary 1 and provide pathways between
binary 0 components at various levels of
the computer system hierarchy
System bus
• A bus that connects major computer
components (processor, memory, I/O)
The most common computer
interconnection structures are
based on the use of one or more
system buses
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Data Bus
Data lines that provide a path for moving data among system
modules
May consist of 32, 64, 128, or more separate lines
The number of lines is referred to as the width of the data bus
The number of lines determines how many bits can be transferred at a
time
The width of the data bus
is a key factor in
determining overall
system performance
+ Address Bus Control Bus
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Used to designate the source or Used to control the access and the
destination of the data on the data use of the data and address lines
bus
If the processor wishes to read a
Because the data and address lines
word of data from memory it puts are shared by all components there
the address of the desired word on must be a means of controlling their
the address lines use
Control signals transmit both
Width determines the maximum
command and timing information
possible memory capacity of the
among system modules
system
Timing signals indicate the validity
Also used to address I/O ports
of data and address information
The higher order bits are used to
select a particular module on the Command signals specify operations
bus and the lower order bits select to be performed
a memory location or I/O port
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Bus Interconnection Scheme
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Bus
Confi
gurati
ons
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Timing of
Synchronous
Bus Operations
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Timing of
Asynchronous
Bus
Operations
