CPU Simulator Step – Wise Notes for ‘read’ & ‘stop’
Step1: In file menu, click on New Text to create your text file. Save it with
extension ‘.a’ which stands for assembly level language.
Step2: In file menu, click on New Machine. This is your machine i.e., CPU
processor. Save it with extension ‘.cpu’. If you somehow forgot or
to write the
extension, it will by default save by ‘.file’ extension, which is also acceptable.
Remember we need both text file and machine to execute our code/program.
Step3: Write code in text file:
1. read ;use ‘;’ for comments
2. stop
Initially, these instructions will not appear green as they are not functional yet.
The user needs to make them functional by giving those instructions, fetch sequence,
etc.
Step4: Creating Registers:
MODIFY HARDWARE MODULES
Type of Module: Register
Name Width Initial Value Read-only
AC 16 0
DR 16 0
IR 16 0
AR 12 0
PC 12 0
Status 2 0
PC (program counter register) – it is for every statement of program
AC (accumulator register) – it accumulates (store/collect) input values
in itself.
IR (instruction register) – it stores instructions of the program
AR(address register) – it stores the address or location of the data in memory
DR (memory data register) - it contains the data to be stored in the computer
memory, or the data after a fetch from the computer memory.
Status (status register) – contains information about state of processor.
Take size of Status register one more than Halt-Bit otherwise the assembler will
give error because halt-bit will specify its (Status
bit. register) least-significant
AR & PC ultimately both will specify same address in memory.
Step5: Creating Memory (RAM):
MODIFY HARDWARE MODULES
Type of Module: RAM
Name Length cellSize
Main 4096 16
How to decide length?
Length = 2width of AR or PC
Length is the size of the memory we are using or we can say total no. of words
CellSize is the size of each word/data.
Step6: Creating Machine Instructions:
MODIFY MACHINE INSTRUCTIONS
On the format tab:-
Instruction Format All fields
4 12 op
read op unused address
unused
‘address’ will be used when data required from memory, for example to do addition we
need operands from memory.
When we don’t require data from memory, we use ‘unused’ which is ignored by the
machine.
Edit fields:
Name Type NumBits DefaultVal Relativity Signed
op Required 4 0 Absolute
address Required 12 0 Absolute
unused Required 12 0 absolute
On the Implementation tab:-
Destination
Double click on ‘io’ microinstruction…
Name Type Buffer Direction
Input AC Integer AC Input
Execute Sequence :(drag & drop)
Input AC [under io] (user defined)
End [under end] (built-in)
Step7: Creating fetch sequence:
MODIFY FETCH SEQUENCE
Microinstructions:
Type of Microinstruction – TransferRtoR
Name Source SrcStartBit Dest DestStartBit numBits
PC AR PC 0 AR 0 12
Type of Microinstruction – memoryAccess
Name Direction Memory Data Address
M[AR] IR Read Main IR AR
What to do Source Destination Position/location
Type of Microinstruction – increment
Name Register overflowBit CarryBit Delta
PC PC+1 PC None None 1
Which register? By how much
Type of Microinstruction – decode
Name ir
DECODE IR
Which register to decode?
Fetch Sequence Implementation: (drag & drop)
PC AR [under TransferRtoR]
M[AR] IR (means ARth position of data in memory)[under memoryAccess]
PC PC + 1 (means to reach or get the next instruction)[under
increment] DECODE [under decode]
END [under End]
Step8: Creating Halt-Bit (for stop): (to terminate)
1. MODIFY HARDWARE MODULES
Type of Module: ConditionBit
Name Register Bit Halt
Halt-Bit Status 1
2. MODIFY MACHINE INSTRUCTIONS
On the format tab:-
Instruction Format All fields
4 12
read
op unused op
address
4 12
unused
stop
op unused
On the implementation tab:-
Type of microinstruction: SetCondBit
Name Bit Value
Halt-bit-enabled-terminate Halt-Bit 1
The same ConditionBit we have created in 1.
Execute Sequence:
Halt-bit-enabled-terminate [under SetCondBit]
End [under End]
Step9: Now, your code is ready to execute and it will appear green.
read
stop
If still code is not green press enter at the end of ‘read’ and
‘stop’ one by one.
NOTE:- All the names are user defined. CPU Sim is Case – Sensitive.
